Rename Cortex-Helios to Neoverse E1
Change-Id: I1adcf195c0ba739002f3a59e805c782dd292ccba Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
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@ -4,28 +4,28 @@
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef CORTEX_HELIOS_H
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#define CORTEX_HELIOS_H
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#ifndef NEOVERSE_E1_H
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#define NEOVERSE_E1_H
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#include <lib/utils_def.h>
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#define CORTEX_HELIOS_MIDR U(0x410FD060)
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#define NEOVERSE_E1_MIDR U(0x410FD060)
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/*******************************************************************************
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* CPU Extended Control register specific definitions.
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******************************************************************************/
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#define CORTEX_HELIOS_ECTLR_EL1 S3_0_C15_C1_4
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#define NEOVERSE_E1_ECTLR_EL1 S3_0_C15_C1_4
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/*******************************************************************************
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* CPU Auxiliary Control register specific definitions.
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******************************************************************************/
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#define CORTEX_HELIOS_CPUACTLR_EL1 S3_0_C15_C1_0
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#define NEOVERSE_E1_CPUACTLR_EL1 S3_0_C15_C1_0
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/*******************************************************************************
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* CPU Power Control register specific definitions.
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******************************************************************************/
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#define CORTEX_HELIOS_CPUPWRCTLR_EL1 S3_0_C15_C2_7
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#define CORTEX_HELIOS_CPUPWRCTLR_EL1_CORE_PWRDN_BIT (U(1) << 0)
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#define NEOVERSE_E1_CPUPWRCTLR_EL1 S3_0_C15_C2_7
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#define NEOVERSE_E1_CPUPWRCTLR_EL1_CORE_PWRDN_BIT (U(1) << 0)
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#endif /* CORTEX_HELIOS_H */
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#endif /* NEOVERSE_E1_H */
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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@ -7,38 +7,38 @@
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#include <asm_macros.S>
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#include <common/bl_common.h>
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#include <common/debug.h>
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#include <cortex_helios.h>
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#include <neoverse_e1.h>
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#include <cpu_macros.S>
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#include <plat_macros.S>
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func cortex_helios_cpu_pwr_dwn
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mrs x0, CORTEX_HELIOS_CPUPWRCTLR_EL1
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orr x0, x0, #CORTEX_HELIOS_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
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msr CORTEX_HELIOS_CPUPWRCTLR_EL1, x0
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func neoverse_e1_cpu_pwr_dwn
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mrs x0, NEOVERSE_E1_CPUPWRCTLR_EL1
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orr x0, x0, #NEOVERSE_E1_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
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msr NEOVERSE_E1_CPUPWRCTLR_EL1, x0
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isb
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ret
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endfunc cortex_helios_cpu_pwr_dwn
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endfunc neoverse_e1_cpu_pwr_dwn
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#if REPORT_ERRATA
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/*
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* Errata printing function for Cortex Helios. Must follow AAPCS.
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* Errata printing function for Neoverse N1. Must follow AAPCS.
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*/
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func cortex_helios_errata_report
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func neoverse_e1_errata_report
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ret
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endfunc cortex_helios_errata_report
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endfunc neoverse_e1_errata_report
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#endif
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.section .rodata.cortex_helios_regs, "aS"
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cortex_helios_regs: /* The ascii list of register names to be reported */
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.section .rodata.neoverse_e1_regs, "aS"
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neoverse_e1_regs: /* The ascii list of register names to be reported */
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.asciz "cpuectlr_el1", ""
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func cortex_helios_cpu_reg_dump
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adr x6, cortex_helios_regs
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mrs x8, CORTEX_HELIOS_ECTLR_EL1
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func neoverse_e1_cpu_reg_dump
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adr x6, neoverse_e1_regs
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mrs x8, NEOVERSE_E1_ECTLR_EL1
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ret
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endfunc cortex_helios_cpu_reg_dump
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endfunc neoverse_e1_cpu_reg_dump
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declare_cpu_ops cortex_helios, CORTEX_HELIOS_MIDR, \
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declare_cpu_ops neoverse_e1, NEOVERSE_E1_MIDR, \
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CPU_NO_RESET_FUNC, \
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cortex_helios_cpu_pwr_dwn
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neoverse_e1_cpu_pwr_dwn
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@ -1,5 +1,5 @@
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#
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# Copyright (c) 2018, Arm Limited. All rights reserved.
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# Copyright (c) 2018-2019, Arm Limited. All rights reserved.
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#
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# SPDX-License-Identifier: BSD-3-Clause
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#
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@ -10,7 +10,7 @@ SGICLARKH_BASE = plat/arm/board/sgiclarkh
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PLAT_INCLUDES += -I${SGICLARKH_BASE}/include/
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SGI_CPU_SOURCES := lib/cpus/aarch64/cortex_helios.S
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SGI_CPU_SOURCES := lib/cpus/aarch64/neoverse_e1.S
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BL1_SOURCES += ${SGI_CPU_SOURCES}
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