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Rename Cortex-Helios to Neoverse E1 

Change-Id: I1adcf195c0ba739002f3a59e805c782dd292ccba
Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
This commit is contained in:
John Tsichritzis 2019-02-19 14:01:55 +00:00
parent fd4bb0ad4b
commit 11088e3924
3 changed files with 28 additions and 28 deletions
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16
include/lib/cpus/aarch64/neoverse_e1.h
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@ -4,28 +4,28 @@
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
*/ */
#ifndef CORTEX_HELIOS_H #ifndef NEOVERSE_E1_H
#define CORTEX_HELIOS_H #define NEOVERSE_E1_H
#include <lib/utils_def.h> #include <lib/utils_def.h>
#define CORTEX_HELIOS_MIDR U(0x410FD060) #define NEOVERSE_E1_MIDR U(0x410FD060)
/******************************************************************************* /*******************************************************************************
* CPU Extended Control register specific definitions. * CPU Extended Control register specific definitions.
******************************************************************************/ ******************************************************************************/
#define CORTEX_HELIOS_ECTLR_EL1 S3_0_C15_C1_4 #define NEOVERSE_E1_ECTLR_EL1 S3_0_C15_C1_4
/******************************************************************************* /*******************************************************************************
* CPU Auxiliary Control register specific definitions. * CPU Auxiliary Control register specific definitions.
******************************************************************************/ ******************************************************************************/
#define CORTEX_HELIOS_CPUACTLR_EL1 S3_0_C15_C1_0 #define NEOVERSE_E1_CPUACTLR_EL1 S3_0_C15_C1_0
/******************************************************************************* /*******************************************************************************
* CPU Power Control register specific definitions. * CPU Power Control register specific definitions.
******************************************************************************/ ******************************************************************************/
#define CORTEX_HELIOS_CPUPWRCTLR_EL1 S3_0_C15_C2_7 #define NEOVERSE_E1_CPUPWRCTLR_EL1 S3_0_C15_C2_7
#define CORTEX_HELIOS_CPUPWRCTLR_EL1_CORE_PWRDN_BIT (U(1) << 0) #define NEOVERSE_E1_CPUPWRCTLR_EL1_CORE_PWRDN_BIT (U(1) << 0)
#endif /* CORTEX_HELIOS_H */ #endif /* NEOVERSE_E1_H */

36
lib/cpus/aarch64/neoverse_e1.S
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@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
* *
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
*/ */
@ -7,38 +7,38 @@
#include <asm_macros.S> #include <asm_macros.S>
#include <common/bl_common.h> #include <common/bl_common.h>
#include <common/debug.h> #include <common/debug.h>
#include <cortex_helios.h> #include <neoverse_e1.h>
#include <cpu_macros.S> #include <cpu_macros.S>
#include <plat_macros.S> #include <plat_macros.S>
func cortex_helios_cpu_pwr_dwn func neoverse_e1_cpu_pwr_dwn
mrs x0, CORTEX_HELIOS_CPUPWRCTLR_EL1 mrs x0, NEOVERSE_E1_CPUPWRCTLR_EL1
orr x0, x0, #CORTEX_HELIOS_CPUPWRCTLR_EL1_CORE_PWRDN_BIT orr x0, x0, #NEOVERSE_E1_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
msr CORTEX_HELIOS_CPUPWRCTLR_EL1, x0 msr NEOVERSE_E1_CPUPWRCTLR_EL1, x0
isb isb
ret ret
endfunc cortex_helios_cpu_pwr_dwn endfunc neoverse_e1_cpu_pwr_dwn
#if REPORT_ERRATA #if REPORT_ERRATA
/* /*
* Errata printing function for Cortex Helios. Must follow AAPCS. * Errata printing function for Neoverse N1. Must follow AAPCS.
*/ */
func cortex_helios_errata_report func neoverse_e1_errata_report
ret ret
endfunc cortex_helios_errata_report endfunc neoverse_e1_errata_report
#endif #endif
.section .rodata.cortex_helios_regs, "aS" .section .rodata.neoverse_e1_regs, "aS"
cortex_helios_regs: /* The ascii list of register names to be reported */ neoverse_e1_regs: /* The ascii list of register names to be reported */
.asciz "cpuectlr_el1", "" .asciz "cpuectlr_el1", ""
func cortex_helios_cpu_reg_dump func neoverse_e1_cpu_reg_dump
adr x6, cortex_helios_regs adr x6, neoverse_e1_regs
mrs x8, CORTEX_HELIOS_ECTLR_EL1 mrs x8, NEOVERSE_E1_ECTLR_EL1
ret ret
endfunc cortex_helios_cpu_reg_dump endfunc neoverse_e1_cpu_reg_dump
declare_cpu_ops cortex_helios, CORTEX_HELIOS_MIDR, \ declare_cpu_ops neoverse_e1, NEOVERSE_E1_MIDR, \
CPU_NO_RESET_FUNC, \ CPU_NO_RESET_FUNC, \
cortex_helios_cpu_pwr_dwn neoverse_e1_cpu_pwr_dwn

4
plat/arm/board/sgiclarkh/platform.mk
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@ -1,5 +1,5 @@
# #
# Copyright (c) 2018, Arm Limited. All rights reserved. # Copyright (c) 2018-2019, Arm Limited. All rights reserved.
# #
# SPDX-License-Identifier: BSD-3-Clause # SPDX-License-Identifier: BSD-3-Clause
# #
@ -10,7 +10,7 @@ SGICLARKH_BASE = plat/arm/board/sgiclarkh
PLAT_INCLUDES += -I${SGICLARKH_BASE}/include/ PLAT_INCLUDES += -I${SGICLARKH_BASE}/include/
SGI_CPU_SOURCES := lib/cpus/aarch64/cortex_helios.S SGI_CPU_SOURCES := lib/cpus/aarch64/neoverse_e1.S
BL1_SOURCES += ${SGI_CPU_SOURCES} BL1_SOURCES += ${SGI_CPU_SOURCES}