From 111a384c90afc629e644e7a8284abbd4311cc6b3 Mon Sep 17 00:00:00 2001 From: Yann Gautier Date: Wed, 12 Feb 2020 09:36:23 +0100 Subject: [PATCH] feat(stm32mp1): remove unsupported features on STM32MP13 * GPIO: On STM32MP13, there are no banks GPIOJ, GPIOK and GPIOZ. * STM32MP13 is a single Cortex-A7 CPU: remove reset from MPU1 and reset from MCU traces * There is no MCU on STM32MP13. Put MCU security management under STM32MP15 flag. * The authentication feature is not supported yet on STM32MP13, put the code under SPM32MP15 flag. * On STM32MP13, the monotonic counter is managed in ROM code, keep the monotonic counter update just for STM32MP15. * SYSCFG: put registers not present on STM32MP13 under STM32MP15 flag, as the code that manages them. * PMIC: use ldo3 during DDR configuration only for STM32MP15 * Reset UART pins on USB boot is no more required. Change-Id: Iceba59484a9bb02828fe7e99f3ecafe69c837bc7 Signed-off-by: Yann Gautier Signed-off-by: Gabriel Fernandez --- drivers/st/pmic/stm32mp_pmic.c | 13 ++++++++++++- plat/st/stm32mp1/bl2_plat_setup.c | 16 +++++++++++++++- plat/st/stm32mp1/platform.mk | 6 +++++- plat/st/stm32mp1/stm32mp1_def.h | 4 ++++ plat/st/stm32mp1/stm32mp1_private.c | 24 ++++++++++++++++++++++++ plat/st/stm32mp1/stm32mp1_syscfg.c | 9 +++++++++ 6 files changed, 69 insertions(+), 3 deletions(-) diff --git a/drivers/st/pmic/stm32mp_pmic.c b/drivers/st/pmic/stm32mp_pmic.c index 7030cf5ce..a1031fdd3 100644 --- a/drivers/st/pmic/stm32mp_pmic.c +++ b/drivers/st/pmic/stm32mp_pmic.c @@ -219,17 +219,20 @@ int pmic_ddr_power_init(enum ddr_type ddr_type) { int status; uint16_t buck3_min_mv; - struct rdev *buck2, *buck3, *ldo3, *vref; + struct rdev *buck2, *buck3, *vref; + struct rdev *ldo3 __unused; buck2 = regulator_get_by_name("buck2"); if (buck2 == NULL) { return -ENOENT; } +#if STM32MP15 ldo3 = regulator_get_by_name("ldo3"); if (ldo3 == NULL) { return -ENOENT; } +#endif vref = regulator_get_by_name("vref_ddr"); if (vref == NULL) { @@ -238,10 +241,12 @@ int pmic_ddr_power_init(enum ddr_type ddr_type) switch (ddr_type) { case STM32MP_DDR3: +#if STM32MP15 status = regulator_set_flag(ldo3, REGUL_SINK_SOURCE); if (status != 0) { return status; } +#endif status = regulator_set_min_voltage(buck2); if (status != 0) { @@ -258,10 +263,12 @@ int pmic_ddr_power_init(enum ddr_type ddr_type) return status; } +#if STM32MP15 status = regulator_enable(ldo3); if (status != 0) { return status; } +#endif break; case STM32MP_LPDDR2: @@ -278,6 +285,7 @@ int pmic_ddr_power_init(enum ddr_type ddr_type) regulator_get_range(buck3, &buck3_min_mv, NULL); +#if STM32MP15 if (buck3_min_mv != 1800) { status = regulator_set_min_voltage(ldo3); if (status != 0) { @@ -289,16 +297,19 @@ int pmic_ddr_power_init(enum ddr_type ddr_type) return status; } } +#endif status = regulator_set_min_voltage(buck2); if (status != 0) { return status; } +#if STM32MP15 status = regulator_enable(ldo3); if (status != 0) { return status; } +#endif status = regulator_enable(buck2); if (status != 0) { diff --git a/plat/st/stm32mp1/bl2_plat_setup.c b/plat/st/stm32mp1/bl2_plat_setup.c index 33ad56f63..20356e412 100644 --- a/plat/st/stm32mp1/bl2_plat_setup.c +++ b/plat/st/stm32mp1/bl2_plat_setup.c @@ -47,7 +47,9 @@ static const char debug_msg[] = { }; #endif +#if STM32MP15 static struct stm32mp_auth_ops stm32mp1_auth_ops; +#endif static void print_reset_reason(void) { @@ -82,6 +84,7 @@ static void print_reset_reason(void) return; } +#if STM32MP15 if ((rstsr & RCC_MP_RSTSCLRR_MCSYSRSTF) != 0U) { if ((rstsr & RCC_MP_RSTSCLRR_PADRSTF) != 0U) { INFO(" System reset generated by MCU (MCSYSRST)\n"); @@ -90,6 +93,7 @@ static void print_reset_reason(void) } return; } +#endif if ((rstsr & RCC_MP_RSTSCLRR_MPSYSRSTF) != 0U) { INFO(" System reset generated by MPU (MPSYSRST)\n"); @@ -116,10 +120,12 @@ static void print_reset_reason(void) return; } +#if STM32MP15 if ((rstsr & RCC_MP_RSTSCLRR_MPUP1RSTF) != 0U) { INFO(" MPU Processor 1 Reset\n"); return; } +#endif if ((rstsr & RCC_MP_RSTSCLRR_PADRSTF) != 0U) { INFO(" Pad Reset from NRST\n"); @@ -171,6 +177,7 @@ void bl2_platform_setup(void) #endif /* STM32MP_USE_STM32IMAGE */ } +#if STM32MP15 static void update_monotonic_counter(void) { uint32_t version; @@ -204,6 +211,7 @@ static void update_monotonic_counter(void) version); } } +#endif void bl2_el3_plat_arch_setup(void) { @@ -271,8 +279,10 @@ void bl2_el3_plat_arch_setup(void) mmio_clrbits_32(rcc_base + RCC_BDCR, RCC_BDCR_VSWRST); } +#if STM32MP15 /* Disable MCKPROT */ mmio_clrbits_32(rcc_base + RCC_TZCR, RCC_TZCR_MCKPROT); +#endif /* * Set minimum reset pulse duration to 31ms for discrete power @@ -307,7 +317,7 @@ void bl2_el3_plat_arch_setup(void) stm32_save_boot_interface(boot_context->boot_interface_selected, boot_context->boot_interface_instance); -#if STM32MP_USB_PROGRAMMER +#if STM32MP_USB_PROGRAMMER && STM32MP15 /* Deconfigure all UART RX pins configured by ROM code */ stm32mp1_deconfigure_uart_pins(); #endif @@ -359,6 +369,7 @@ skip_console_init: } } +#if STM32MP15 if (stm32mp_is_auth_supported()) { stm32mp1_auth_ops.check_key = boot_context->bootrom_ecdsa_check_key; @@ -367,12 +378,15 @@ skip_console_init: stm32mp_init_auth(&stm32mp1_auth_ops); } +#endif stm32mp1_arch_security_setup(); print_reset_reason(); +#if STM32MP15 update_monotonic_counter(); +#endif stm32mp1_syscfg_enable_io_compensation_finish(); diff --git a/plat/st/stm32mp1/platform.mk b/plat/st/stm32mp1/platform.mk index 6b8b71250..735a58f9b 100644 --- a/plat/st/stm32mp1/platform.mk +++ b/plat/st/stm32mp1/platform.mk @@ -303,9 +303,13 @@ BL2_SOURCES += drivers/io/io_block.c \ drivers/io/io_mtd.c \ drivers/io/io_storage.c \ drivers/st/crypto/stm32_hash.c \ - plat/st/common/stm32mp_auth.c \ plat/st/stm32mp1/bl2_plat_setup.c + +ifeq ($(STM32MP15),1) +BL2_SOURCES += plat/st/common/stm32mp_auth.c +endif + ifneq ($(filter 1,${STM32MP_EMMC} ${STM32MP_SDMMC}),) BL2_SOURCES += drivers/mmc/mmc.c \ drivers/partition/gpt.c \ diff --git a/plat/st/stm32mp1/stm32mp1_def.h b/plat/st/stm32mp1/stm32mp1_def.h index 1d5580752..094693689 100644 --- a/plat/st/stm32mp1/stm32mp1_def.h +++ b/plat/st/stm32mp1/stm32mp1_def.h @@ -182,9 +182,11 @@ enum ddr_type { #define GPIOG_BASE U(0x50008000) #define GPIOH_BASE U(0x50009000) #define GPIOI_BASE U(0x5000A000) +#if STM32MP15 #define GPIOJ_BASE U(0x5000B000) #define GPIOK_BASE U(0x5000C000) #define GPIOZ_BASE U(0x54004000) +#endif #define GPIO_BANK_OFFSET U(0x1000) /* Bank IDs used in GPIO driver API */ @@ -197,11 +199,13 @@ enum ddr_type { #define GPIO_BANK_G U(6) #define GPIO_BANK_H U(7) #define GPIO_BANK_I U(8) +#if STM32MP15 #define GPIO_BANK_J U(9) #define GPIO_BANK_K U(10) #define GPIO_BANK_Z U(25) #define STM32MP_GPIOZ_PIN_MAX_COUNT 8 +#endif /******************************************************************************* * STM32MP1 UART diff --git a/plat/st/stm32mp1/stm32mp1_private.c b/plat/st/stm32mp1/stm32mp1_private.c index 1125a69e0..8c27af2ca 100644 --- a/plat/st/stm32mp1/stm32mp1_private.c +++ b/plat/st/stm32mp1/stm32mp1_private.c @@ -111,42 +111,62 @@ void configure_mmu(void) uintptr_t stm32_get_gpio_bank_base(unsigned int bank) { +#if STM32MP13 + assert(GPIO_BANK_A == 0 && bank <= GPIO_BANK_I); +#endif +#if STM32MP15 if (bank == GPIO_BANK_Z) { return GPIOZ_BASE; } assert(GPIO_BANK_A == 0 && bank <= GPIO_BANK_K); +#endif return GPIOA_BASE + (bank * GPIO_BANK_OFFSET); } uint32_t stm32_get_gpio_bank_offset(unsigned int bank) { +#if STM32MP13 + assert(GPIO_BANK_A == 0 && bank <= GPIO_BANK_I); +#endif +#if STM32MP15 if (bank == GPIO_BANK_Z) { return 0; } assert(GPIO_BANK_A == 0 && bank <= GPIO_BANK_K); +#endif return bank * GPIO_BANK_OFFSET; } bool stm32_gpio_is_secure_at_reset(unsigned int bank) { +#if STM32MP13 + return true; +#endif +#if STM32MP15 if (bank == GPIO_BANK_Z) { return true; } return false; +#endif } unsigned long stm32_get_gpio_bank_clock(unsigned int bank) { +#if STM32MP13 + assert(GPIO_BANK_A == 0 && bank <= GPIO_BANK_I); +#endif +#if STM32MP15 if (bank == GPIO_BANK_Z) { return GPIOZ; } assert(GPIO_BANK_A == 0 && bank <= GPIO_BANK_K); +#endif return GPIOA + (bank - GPIO_BANK_A); } @@ -163,11 +183,15 @@ int stm32_get_gpio_bank_pinctrl_node(void *fdt, unsigned int bank) case GPIO_BANK_G: case GPIO_BANK_H: case GPIO_BANK_I: +#if STM32MP15 case GPIO_BANK_J: case GPIO_BANK_K: +#endif return fdt_path_offset(fdt, "/soc/pin-controller"); +#if STM32MP15 case GPIO_BANK_Z: return fdt_path_offset(fdt, "/soc/pin-controller-z"); +#endif default: panic(); } diff --git a/plat/st/stm32mp1/stm32mp1_syscfg.c b/plat/st/stm32mp1/stm32mp1_syscfg.c index 3f34af15b..6d24b0e85 100644 --- a/plat/st/stm32mp1/stm32mp1_syscfg.c +++ b/plat/st/stm32mp1/stm32mp1_syscfg.c @@ -19,8 +19,10 @@ * SYSCFG REGISTER OFFSET (base relative) */ #define SYSCFG_BOOTR 0x00U +#if STM32MP15 #define SYSCFG_IOCTRLSETR 0x18U #define SYSCFG_ICNR 0x1CU +#endif #define SYSCFG_CMPCR 0x20U #define SYSCFG_CMPENSETR 0x24U #define SYSCFG_CMPENCLRR 0x28U @@ -32,8 +34,11 @@ * SYSCFG_BOOTR Register */ #define SYSCFG_BOOTR_BOOT_MASK GENMASK(2, 0) +#if STM32MP15 #define SYSCFG_BOOTR_BOOTPD_MASK GENMASK(6, 4) #define SYSCFG_BOOTR_BOOTPD_SHIFT 4 +#endif + /* * SYSCFG_IOCTRLSETR Register */ @@ -106,12 +111,14 @@ static void disable_io_comp_cell(uintptr_t cmpcr_off) static void enable_high_speed_mode_low_voltage(void) { +#if STM32MP15 mmio_write_32(SYSCFG_BASE + SYSCFG_IOCTRLSETR, SYSCFG_IOCTRLSETR_HSLVEN_TRACE | SYSCFG_IOCTRLSETR_HSLVEN_QUADSPI | SYSCFG_IOCTRLSETR_HSLVEN_ETH | SYSCFG_IOCTRLSETR_HSLVEN_SDMMC | SYSCFG_IOCTRLSETR_HSLVEN_SPI); +#endif } static void stm32mp1_syscfg_set_hslv(void) @@ -165,6 +172,7 @@ static void stm32mp1_syscfg_set_hslv(void) void stm32mp1_syscfg_init(void) { +#if STM32MP15 uint32_t bootr; /* @@ -178,6 +186,7 @@ void stm32mp1_syscfg_init(void) SYSCFG_BOOTR_BOOT_MASK; mmio_clrsetbits_32(SYSCFG_BASE + SYSCFG_BOOTR, SYSCFG_BOOTR_BOOTPD_MASK, bootr << SYSCFG_BOOTR_BOOTPD_SHIFT); +#endif stm32mp1_syscfg_set_hslv();