From 115041633d662ea8f2d3952f10c6e39ad5f5ef22 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Thu, 2 Apr 2020 15:35:19 +0900 Subject: [PATCH] locks: bakery: use is_dcache_enabled() helper bakery_lock_normal.c uses the raw register accessor, read_sctlr(_el3) to check whether the dcache is enabled. Using is_dcache_enabled() is cleaner, and a good abstraction for the library code like this. A problem is is_dcache_enabled() is declared in the local header, lib/xlat_tables_v2/xlat_tables_private.h I searched for a good place to declare this helper. Moving it to arch_helpers.h, closed to cache operation helpers, looks good enough to me. I also changed the type of 'is_cached' to bool for consistency, and to avoid MISRA warnings. Change-Id: I9b016f67bc8eade25c316aa9c0db0fa4cd375b79 Signed-off-by: Masahiro Yamada --- include/arch/aarch32/arch_helpers.h | 4 +++- include/arch/aarch64/arch_helpers.h | 1 + lib/locks/bakery/bakery_lock_normal.c | 21 +++++++-------------- lib/xlat_tables_v2/xlat_tables_private.h | 5 +---- 4 files changed, 12 insertions(+), 19 deletions(-) diff --git a/include/arch/aarch32/arch_helpers.h b/include/arch/aarch32/arch_helpers.h index cbac84b93..a90b2a54c 100644 --- a/include/arch/aarch32/arch_helpers.h +++ b/include/arch/aarch32/arch_helpers.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -8,6 +8,7 @@ #define ARCH_HELPERS_H #include +#include #include #include @@ -178,6 +179,7 @@ static inline void _op ## _type(u_register_t v) \ void flush_dcache_range(uintptr_t addr, size_t size); void clean_dcache_range(uintptr_t addr, size_t size); void inv_dcache_range(uintptr_t addr, size_t size); +bool is_dcache_enabled(void); void dcsw_op_louis(u_register_t op_type); void dcsw_op_all(u_register_t op_type); diff --git a/include/arch/aarch64/arch_helpers.h b/include/arch/aarch64/arch_helpers.h index 7c30758d0..669a1403c 100644 --- a/include/arch/aarch64/arch_helpers.h +++ b/include/arch/aarch64/arch_helpers.h @@ -226,6 +226,7 @@ DEFINE_SYSOP_PARAM_FUNC(xpaci) void flush_dcache_range(uintptr_t addr, size_t size); void clean_dcache_range(uintptr_t addr, size_t size); void inv_dcache_range(uintptr_t addr, size_t size); +bool is_dcache_enabled(void); void dcsw_op_louis(u_register_t op_type); void dcsw_op_all(u_register_t op_type); diff --git a/lib/locks/bakery/bakery_lock_normal.c b/lib/locks/bakery/bakery_lock_normal.c index 0605fceb9..7d35dea66 100644 --- a/lib/locks/bakery/bakery_lock_normal.c +++ b/lib/locks/bakery/bakery_lock_normal.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved. * Copyright (c) 2020, NVIDIA Corporation. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -84,7 +84,7 @@ static inline void read_cache_op(uintptr_t addr, bool cached) /* Helper function to check if the lock is acquired */ static inline bool is_lock_acquired(const bakery_info_t *my_bakery_info, - int is_cached) + bool is_cached) { /* * Even though lock data is updated only by the owning cpu and @@ -99,7 +99,7 @@ static inline bool is_lock_acquired(const bakery_info_t *my_bakery_info, } static unsigned int bakery_get_ticket(bakery_lock_t *lock, - unsigned int me, int is_cached) + unsigned int me, bool is_cached) { unsigned int my_ticket, their_ticket; unsigned int they; @@ -164,17 +164,14 @@ static unsigned int bakery_get_ticket(bakery_lock_t *lock, void bakery_lock_get(bakery_lock_t *lock) { - unsigned int they, me, is_cached; + unsigned int they, me; unsigned int my_ticket, my_prio, their_ticket; bakery_info_t *their_bakery_info; unsigned int their_bakery_data; + bool is_cached; me = plat_my_core_pos(); -#ifdef __aarch64__ - is_cached = read_sctlr_el3() & SCTLR_C_BIT; -#else - is_cached = read_sctlr() & SCTLR_C_BIT; -#endif + is_cached = is_dcache_enabled(); /* Get a ticket */ my_ticket = bakery_get_ticket(lock, me, is_cached); @@ -232,11 +229,7 @@ void bakery_lock_get(bakery_lock_t *lock) void bakery_lock_release(bakery_lock_t *lock) { bakery_info_t *my_bakery_info; -#ifdef __aarch64__ - unsigned int is_cached = read_sctlr_el3() & SCTLR_C_BIT; -#else - unsigned int is_cached = read_sctlr() & SCTLR_C_BIT; -#endif + bool is_cached = is_dcache_enabled(); my_bakery_info = get_bakery_info(plat_my_core_pos(), lock); diff --git a/lib/xlat_tables_v2/xlat_tables_private.h b/lib/xlat_tables_v2/xlat_tables_private.h index 70ef39523..863470cf3 100644 --- a/lib/xlat_tables_v2/xlat_tables_private.h +++ b/lib/xlat_tables_v2/xlat_tables_private.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -99,9 +99,6 @@ unsigned long long xlat_arch_get_max_supported_pa(void); */ bool is_mmu_enabled_ctx(const xlat_ctx_t *ctx); -/* Returns true if the data cache is enabled at the current EL. */ -bool is_dcache_enabled(void); - /* * Returns minimum virtual address space size supported by the architecture */