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Tegra186: sip_calls: fix defects flagged by MISRA scan 

Main fixes:

Added explicit casts (e.g. 0U) to integers in order for them to be
compatible with whatever operation they're used in [Rule 10.1]

Convert object type to match the type of function parameters
[Rule 10.3]

Force operands of an operator to the same type category [Rule 10.4]

Expressions resulting from the expansion of macro parameters
shall be enclosed in parentheses[Rule 20.7]

Change-Id: Ibdae1d18d299562ca2b96b2318b914601c9926b1
Signed-off-by: Anthony Zhou <anzhou@nvidia.com>
This commit is contained in:
Anthony Zhou 2017-02-28 14:47:44 +08:00 committed by Varun Wadekar
parent f0bfe15b81
commit 11c5b2733a
1 changed files with 39 additions and 32 deletions
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71
plat/nvidia/tegra/soc/t186/plat_sip_calls.c
View File

@ -23,7 +23,7 @@
/*******************************************************************************
* Offset to read the ref_clk counter value
******************************************************************************/
#define REF_CLK_OFFSET 4
#define REF_CLK_OFFSET 4ULL
/*******************************************************************************
* Tegra186 SiP SMCs
@ -35,7 +35,7 @@
#define TEGRA_SIP_MCE_CMD_READ_CSTATE_STATS 0xC2FFFF03
#define TEGRA_SIP_MCE_CMD_WRITE_CSTATE_STATS 0xC2FFFF04
#define TEGRA_SIP_MCE_CMD_IS_SC7_ALLOWED 0xC2FFFF05
#define TEGRA_SIP_MCE_CMD_ONLINE_CORE 0xC2FFFF06
#define TEGRA_SIP_MCE_CMD_CC3_CTRL 0xC2FFFF07
#define TEGRA_SIP_MCE_CMD_ECHO_DATA 0xC2FFFF08
#define TEGRA_SIP_MCE_CMD_READ_VERSIONS 0xC2FFFF09
@ -52,7 +52,7 @@
/*******************************************************************************
* This function is responsible for handling all T186 SiP calls
******************************************************************************/
int plat_sip_handler(uint32_t smc_fid,
int32_t plat_sip_handler(uint32_t smc_fid,
uint64_t x1,
uint64_t x2,
uint64_t x3,
@ -61,24 +61,30 @@ int plat_sip_handler(uint32_t smc_fid,
void *handle,
uint64_t flags)
{
int mce_ret;
int impl, cpu;
int32_t mce_ret, ret = 0;
uint32_t impl, cpu;
uint32_t base, core_clk_ctr, ref_clk_ctr;
uint32_t local_smc_fid = smc_fid;
uint64_t local_x1 = x1, local_x2 = x2, local_x3 = x3;
(void)x4;
(void)cookie;
(void)flags;
if (((smc_fid >> FUNCID_CC_SHIFT) & FUNCID_CC_MASK) == SMC_32) {
/* 32-bit function, clear top parameter bits */
x1 = (uint32_t)x1;
x2 = (uint32_t)x2;
x3 = (uint32_t)x3;
local_x1 = (uint32_t)x1;
local_x2 = (uint32_t)x2;
local_x3 = (uint32_t)x3;
}
/*
* Convert SMC FID to SMC64, to support SMC32/SMC64 configurations
*/
smc_fid |= (SMC_64 << FUNCID_CC_SHIFT);
local_smc_fid |= (SMC_64 << FUNCID_CC_SHIFT);
switch (smc_fid) {
switch (local_smc_fid) {
/*
* Micro Coded Engine (MCE) commands reside in the 0x82FFFF00 -
* 0x82FFFFFF SiP SMC space
@ -103,14 +109,13 @@ int plat_sip_handler(uint32_t smc_fid,
case TEGRA_SIP_MCE_CMD_MISC_CCPLEX:
/* clean up the high bits */
smc_fid &= MCE_CMD_MASK;
local_smc_fid &= MCE_CMD_MASK;
/* execute the command and store the result */
mce_ret = mce_command_handler(smc_fid, x1, x2, x3);
write_ctx_reg(get_gpregs_ctx(handle), CTX_GPREG_X0,
(uint64_t)mce_ret);
return 0;
mce_ret = mce_command_handler(local_smc_fid, local_x1, local_x2, local_x3);
write_ctx_reg(get_gpregs_ctx(handle),
CTX_GPREG_X0, (uint64_t)(mce_ret));
break;
/*
* This function ID reads the Activity monitor's core/ref clock
@ -125,28 +130,30 @@ int plat_sip_handler(uint32_t smc_fid,
impl = ((uint32_t)x2 >> MIDR_IMPL_SHIFT) & MIDR_IMPL_MASK;
/* sanity check target CPU number */
if (cpu > PLATFORM_MAX_CPUS_PER_CLUSTER)
return -EINVAL;
if (cpu > (uint32_t)PLATFORM_MAX_CPUS_PER_CLUSTER) {
ret = -EINVAL;
} else {
/* get the base address for the current CPU */
base = (impl == DENVER_IMPL) ? TEGRA_DENVER_ACTMON_CTR_BASE :
TEGRA_ARM_ACTMON_CTR_BASE;
/* get the base address for the current CPU */
base = (impl == DENVER_IMPL) ? TEGRA_DENVER_ACTMON_CTR_BASE :
TEGRA_ARM_ACTMON_CTR_BASE;
/* read the clock counter values */
core_clk_ctr = mmio_read_32(base + (8ULL * cpu));
ref_clk_ctr = mmio_read_32(base + (8ULL * cpu) + REF_CLK_OFFSET);
/* read the clock counter values */
core_clk_ctr = mmio_read_32(base + (8 * cpu));
ref_clk_ctr = mmio_read_32(base + (8 * cpu) + REF_CLK_OFFSET);
/* return the counter values as two different parameters */
write_ctx_reg(get_gpregs_ctx(handle),
CTX_GPREG_X1, (core_clk_ctr));
write_ctx_reg(get_gpregs_ctx(handle),
CTX_GPREG_X2, (ref_clk_ctr));
}
/* return the counter values as two different parameters */
write_ctx_reg(get_gpregs_ctx(handle), CTX_GPREG_X1,
(uint64_t)core_clk_ctr);
write_ctx_reg(get_gpregs_ctx(handle), CTX_GPREG_X2,
(uint64_t)ref_clk_ctr);
return 0;
break;
default:
ret = -ENOTSUP;
break;
}
return -ENOTSUP;
return ret;
}