Tegra186: sip_calls: fix defects flagged by MISRA scan
Main fixes: Added explicit casts (e.g. 0U) to integers in order for them to be compatible with whatever operation they're used in [Rule 10.1] Convert object type to match the type of function parameters [Rule 10.3] Force operands of an operator to the same type category [Rule 10.4] Expressions resulting from the expansion of macro parameters shall be enclosed in parentheses[Rule 20.7] Change-Id: Ibdae1d18d299562ca2b96b2318b914601c9926b1 Signed-off-by: Anthony Zhou <anzhou@nvidia.com>
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@ -23,7 +23,7 @@
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/*******************************************************************************
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/*******************************************************************************
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* Offset to read the ref_clk counter value
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* Offset to read the ref_clk counter value
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******************************************************************************/
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******************************************************************************/
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#define REF_CLK_OFFSET 4
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#define REF_CLK_OFFSET 4ULL
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/*******************************************************************************
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/*******************************************************************************
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* Tegra186 SiP SMCs
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* Tegra186 SiP SMCs
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@ -35,7 +35,7 @@
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#define TEGRA_SIP_MCE_CMD_READ_CSTATE_STATS 0xC2FFFF03
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#define TEGRA_SIP_MCE_CMD_READ_CSTATE_STATS 0xC2FFFF03
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#define TEGRA_SIP_MCE_CMD_WRITE_CSTATE_STATS 0xC2FFFF04
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#define TEGRA_SIP_MCE_CMD_WRITE_CSTATE_STATS 0xC2FFFF04
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#define TEGRA_SIP_MCE_CMD_IS_SC7_ALLOWED 0xC2FFFF05
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#define TEGRA_SIP_MCE_CMD_IS_SC7_ALLOWED 0xC2FFFF05
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#define TEGRA_SIP_MCE_CMD_ONLINE_CORE 0xC2FFFF06
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#define TEGRA_SIP_MCE_CMD_CC3_CTRL 0xC2FFFF07
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#define TEGRA_SIP_MCE_CMD_CC3_CTRL 0xC2FFFF07
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#define TEGRA_SIP_MCE_CMD_ECHO_DATA 0xC2FFFF08
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#define TEGRA_SIP_MCE_CMD_ECHO_DATA 0xC2FFFF08
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#define TEGRA_SIP_MCE_CMD_READ_VERSIONS 0xC2FFFF09
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#define TEGRA_SIP_MCE_CMD_READ_VERSIONS 0xC2FFFF09
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@ -52,7 +52,7 @@
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/*******************************************************************************
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/*******************************************************************************
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* This function is responsible for handling all T186 SiP calls
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* This function is responsible for handling all T186 SiP calls
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******************************************************************************/
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******************************************************************************/
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int plat_sip_handler(uint32_t smc_fid,
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int32_t plat_sip_handler(uint32_t smc_fid,
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uint64_t x1,
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uint64_t x1,
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uint64_t x2,
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uint64_t x2,
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uint64_t x3,
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uint64_t x3,
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@ -61,24 +61,30 @@ int plat_sip_handler(uint32_t smc_fid,
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void *handle,
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void *handle,
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uint64_t flags)
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uint64_t flags)
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{
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{
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int mce_ret;
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int32_t mce_ret, ret = 0;
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int impl, cpu;
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uint32_t impl, cpu;
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uint32_t base, core_clk_ctr, ref_clk_ctr;
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uint32_t base, core_clk_ctr, ref_clk_ctr;
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uint32_t local_smc_fid = smc_fid;
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uint64_t local_x1 = x1, local_x2 = x2, local_x3 = x3;
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(void)x4;
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(void)cookie;
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(void)flags;
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if (((smc_fid >> FUNCID_CC_SHIFT) & FUNCID_CC_MASK) == SMC_32) {
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if (((smc_fid >> FUNCID_CC_SHIFT) & FUNCID_CC_MASK) == SMC_32) {
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/* 32-bit function, clear top parameter bits */
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/* 32-bit function, clear top parameter bits */
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x1 = (uint32_t)x1;
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local_x1 = (uint32_t)x1;
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x2 = (uint32_t)x2;
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local_x2 = (uint32_t)x2;
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x3 = (uint32_t)x3;
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local_x3 = (uint32_t)x3;
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}
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}
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/*
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/*
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* Convert SMC FID to SMC64, to support SMC32/SMC64 configurations
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* Convert SMC FID to SMC64, to support SMC32/SMC64 configurations
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*/
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*/
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smc_fid |= (SMC_64 << FUNCID_CC_SHIFT);
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local_smc_fid |= (SMC_64 << FUNCID_CC_SHIFT);
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switch (smc_fid) {
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switch (local_smc_fid) {
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/*
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/*
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* Micro Coded Engine (MCE) commands reside in the 0x82FFFF00 -
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* Micro Coded Engine (MCE) commands reside in the 0x82FFFF00 -
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* 0x82FFFFFF SiP SMC space
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* 0x82FFFFFF SiP SMC space
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@ -103,14 +109,13 @@ int plat_sip_handler(uint32_t smc_fid,
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case TEGRA_SIP_MCE_CMD_MISC_CCPLEX:
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case TEGRA_SIP_MCE_CMD_MISC_CCPLEX:
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/* clean up the high bits */
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/* clean up the high bits */
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smc_fid &= MCE_CMD_MASK;
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local_smc_fid &= MCE_CMD_MASK;
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/* execute the command and store the result */
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/* execute the command and store the result */
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mce_ret = mce_command_handler(smc_fid, x1, x2, x3);
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mce_ret = mce_command_handler(local_smc_fid, local_x1, local_x2, local_x3);
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write_ctx_reg(get_gpregs_ctx(handle), CTX_GPREG_X0,
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write_ctx_reg(get_gpregs_ctx(handle),
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(uint64_t)mce_ret);
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CTX_GPREG_X0, (uint64_t)(mce_ret));
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break;
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return 0;
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/*
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/*
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* This function ID reads the Activity monitor's core/ref clock
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* This function ID reads the Activity monitor's core/ref clock
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@ -125,28 +130,30 @@ int plat_sip_handler(uint32_t smc_fid,
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impl = ((uint32_t)x2 >> MIDR_IMPL_SHIFT) & MIDR_IMPL_MASK;
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impl = ((uint32_t)x2 >> MIDR_IMPL_SHIFT) & MIDR_IMPL_MASK;
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/* sanity check target CPU number */
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/* sanity check target CPU number */
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if (cpu > PLATFORM_MAX_CPUS_PER_CLUSTER)
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if (cpu > (uint32_t)PLATFORM_MAX_CPUS_PER_CLUSTER) {
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return -EINVAL;
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ret = -EINVAL;
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} else {
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/* get the base address for the current CPU */
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/* get the base address for the current CPU */
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base = (impl == DENVER_IMPL) ? TEGRA_DENVER_ACTMON_CTR_BASE :
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base = (impl == DENVER_IMPL) ? TEGRA_DENVER_ACTMON_CTR_BASE :
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TEGRA_ARM_ACTMON_CTR_BASE;
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TEGRA_ARM_ACTMON_CTR_BASE;
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/* read the clock counter values */
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/* read the clock counter values */
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core_clk_ctr = mmio_read_32(base + (8 * cpu));
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core_clk_ctr = mmio_read_32(base + (8ULL * cpu));
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ref_clk_ctr = mmio_read_32(base + (8 * cpu) + REF_CLK_OFFSET);
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ref_clk_ctr = mmio_read_32(base + (8ULL * cpu) + REF_CLK_OFFSET);
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/* return the counter values as two different parameters */
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/* return the counter values as two different parameters */
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write_ctx_reg(get_gpregs_ctx(handle), CTX_GPREG_X1,
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write_ctx_reg(get_gpregs_ctx(handle),
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(uint64_t)core_clk_ctr);
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CTX_GPREG_X1, (core_clk_ctr));
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write_ctx_reg(get_gpregs_ctx(handle), CTX_GPREG_X2,
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write_ctx_reg(get_gpregs_ctx(handle),
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(uint64_t)ref_clk_ctr);
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CTX_GPREG_X2, (ref_clk_ctr));
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}
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return 0;
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break;
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default:
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default:
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ret = -ENOTSUP;
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break;
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break;
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}
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}
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return -ENOTSUP;
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return ret;
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}
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}
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