juno: Initialise PCIe
Signed-off-by: Jon Medhurst <tixy@linaro.org>
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06f1af9111
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@ -174,6 +174,18 @@ static void init_tzc400(void)
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);
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);
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}
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}
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#define PCIE_SECURE_REG 0x3000
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#define PCIE_SEC_ACCESS_MASK ((1 << 0) | (1 << 1)) /* REG and MEM access bits */
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static void init_pcie(void)
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{
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/*
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* PCIE Root Complex Security settings to enable non-secure
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* access to config registers.
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*/
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mmio_write_32(PCIE_CONTROL_BASE + PCIE_SECURE_REG, PCIE_SEC_ACCESS_MASK);
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}
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/*******************************************************************************
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/*******************************************************************************
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* Function which will perform any remaining platform-specific setup that can
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* Function which will perform any remaining platform-specific setup that can
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@ -183,6 +195,7 @@ void bl1_platform_setup(void)
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{
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{
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init_nic400();
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init_nic400();
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init_tzc400();
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init_tzc400();
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init_pcie();
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/* Initialise the IO layer and register platform IO devices */
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/* Initialise the IO layer and register platform IO devices */
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io_setup();
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io_setup();
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@ -119,6 +119,7 @@
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#define DEVICE1_BASE 0x40000000
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#define DEVICE1_BASE 0x40000000
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#define DEVICE1_SIZE 0x40000000
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#define DEVICE1_SIZE 0x40000000
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#define SOC_NIC400_BASE 0x7fd00000
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#define SOC_NIC400_BASE 0x7fd00000
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#define PCIE_CONTROL_BASE 0x7ff20000
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#define DRAM_BASE 0x80000000
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#define DRAM_BASE 0x80000000
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#define DRAM_SIZE 0x80000000
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#define DRAM_SIZE 0x80000000
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