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Merge changes from topic "rdn1edge_dual" into integration 

* changes:
  board/rde1edge: fix incorrect topology tree description
  plat/arm/sgi: introduce number of chips macro
This commit is contained in:
Sandrine Bailleux 2020-02-07 14:13:30 +00:00 committed by TrustedFirmware Code Review
parent d6b44b10e9 4e95010937
commit 129f80d674
6 changed files with 30 additions and 3 deletions
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5
docs/plat/arm/arm-build-options.rst
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@ -114,6 +114,11 @@ Arm CSS Platform-Specific Build Options
management operations and for SCP RAM Firmware transfer. If this option
is set to 1, then SCMI/SDS drivers will be used. Default is 0.
- ``CSS_SGI_CHIP_COUNT``: Configures the number of chips on a SGI/RD platform
which supports multi-chip operation. If ``CSS_SGI_CHIP_COUNT`` is set to any
valid value greater than 1, the platform code performs required configuration
to support multi-chip operation.
--------------
*Copyright (c) 2019-2020, Arm Limited. All rights reserved.*

5
plat/arm/board/rde1edge/platform.mk
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@ -47,4 +47,9 @@ NT_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_nt_fw_config.dtb
# Add the NT_FW_CONFIG to FIP and specify the same to certtool
$(eval $(call TOOL_ADD_PAYLOAD,${NT_FW_CONFIG},--nt-fw-config))
ifneq ($(CSS_SGI_CHIP_COUNT),1)
$(error "Chip count for RDE1Edge should be 1, currently set to \
${CSS_SGI_CHIP_COUNT}.")
endif
override CTX_INCLUDE_AARCH32_REGS := 0

9
plat/arm/board/rde1edge/rde1edge_topology.c
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@ -7,12 +7,15 @@
#include <plat/arm/common/plat_arm.h>
/******************************************************************************
* The power domain tree descriptor.
* The power domain tree descriptor. RD-E1-Edge platform consists of two
* clusters with eight CPUs in each cluster. The CPUs are multi-threaded with
* two threads per CPU.
******************************************************************************/
static const unsigned char rde1edge_pd_tree_desc[] = {
CSS_SGI_CHIP_COUNT,
PLAT_ARM_CLUSTER_COUNT,
CSS_SGI_MAX_CPUS_PER_CLUSTER,
CSS_SGI_MAX_CPUS_PER_CLUSTER
CSS_SGI_MAX_CPUS_PER_CLUSTER * CSS_SGI_MAX_PE_PER_CPU,
CSS_SGI_MAX_CPUS_PER_CLUSTER * CSS_SGI_MAX_PE_PER_CPU
};
/******************************************************************************

5
plat/arm/board/rdn1edge/platform.mk
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@ -47,4 +47,9 @@ NT_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_nt_fw_config.dtb
# Add the NT_FW_CONFIG to FIP and specify the same to certtool
$(eval $(call TOOL_ADD_PAYLOAD,${NT_FW_CONFIG},--nt-fw-config))
ifneq ($(CSS_SGI_CHIP_COUNT),1)
$(error "Chip count for RDN1Edge should be 1, currently set to \
${CSS_SGI_CHIP_COUNT}.")
endif
override CTX_INCLUDE_AARCH32_REGS := 0

5
plat/arm/board/sgi575/platform.mk
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@ -46,3 +46,8 @@ NT_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_nt_fw_config.dtb
# Add the NT_FW_CONFIG to FIP and specify the same to certtool
$(eval $(call TOOL_ADD_PAYLOAD,${NT_FW_CONFIG},--nt-fw-config))
ifneq ($(CSS_SGI_CHIP_COUNT),1)
$(error "Chip count for SGI575 should be 1, currently set to \
${CSS_SGI_CHIP_COUNT}.")
endif

4
plat/arm/css/sgi/sgi-common.mk
View File

@ -16,6 +16,8 @@ EL3_EXCEPTION_HANDLING := 0
HANDLE_EA_EL3_FIRST := 0
CSS_SGI_CHIP_COUNT := 1
INTERCONNECT_SOURCES := ${CSS_ENT_BASE}/sgi_interconnect.c
PLAT_INCLUDES += -I${CSS_ENT_BASE}/include
@ -52,6 +54,8 @@ endif
$(eval $(call add_define,SGI_PLAT))
$(eval $(call add_define,CSS_SGI_CHIP_COUNT))
override CSS_LOAD_SCP_IMAGES := 0
override NEED_BL2U := no
override ARM_BL31_IN_DRAM := 1