stm32mp1: Add support for raw NAND boot device
STM32MP1 platform is able to boot from raw NAND devices. These modifications add this support using the new raw NAND framework. Change-Id: I9e9c2b03930f98a5ac23f2b6b41945bef43e5043 Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
This commit is contained in:
Lionel Debieve
parent
695f7df852
commit
12e21dfde2
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@ -14,11 +14,14 @@
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#include <drivers/io/io_block.h>
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#include <drivers/io/io_driver.h>
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#include <drivers/io/io_dummy.h>
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#include <drivers/io/io_mtd.h>
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#include <drivers/io/io_storage.h>
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#include <drivers/mmc.h>
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#include <drivers/partition/partition.h>
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#include <drivers/raw_nand.h>
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#include <drivers/st/io_mmc.h>
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#include <drivers/st/io_stm32image.h>
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#include <drivers/st/stm32_fmc2_nand.h>
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#include <drivers/st/stm32_sdmmc2.h>
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#include <lib/mmio.h>
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#include <lib/utils.h>
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@ -56,6 +59,17 @@ static const io_block_dev_spec_t mmc_block_dev_spec = {
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static const io_dev_connector_t *mmc_dev_con;
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#endif /* STM32MP_SDMMC || STM32MP_EMMC */
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#if STM32MP_RAW_NAND
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static io_mtd_dev_spec_t nand_dev_spec = {
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.ops = {
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.init = nand_raw_init,
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.read = nand_read,
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},
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};
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static const io_dev_connector_t *nand_dev_con;
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#endif
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#ifdef AARCH32_SP_OPTEE
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static const struct stm32image_part_info optee_header_partition_spec = {
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.name = OPTEE_HEADER_IMAGE_NAME,
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@ -209,6 +223,9 @@ static void print_boot_device(boot_api_context_t *boot_context)
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case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_EMMC:
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INFO("Using EMMC\n");
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break;
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case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NAND_FMC:
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INFO("Using FMC NAND\n");
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break;
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default:
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ERROR("Boot interface not found\n");
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panic();
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@ -312,6 +329,59 @@ static void boot_mmc(enum mmc_device_type mmc_dev_type,
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}
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#endif /* STM32MP_SDMMC || STM32MP_EMMC */
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#if STM32MP_RAW_NAND
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static void boot_fmc2_nand(boot_api_context_t *boot_context)
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{
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int io_result __unused;
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uint8_t idx;
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struct stm32image_part_info *part;
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io_result = stm32_fmc2_init();
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assert(io_result == 0);
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/* Register the IO device on this platform */
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io_result = register_io_dev_mtd(&nand_dev_con);
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assert(io_result == 0);
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/* Open connections to device */
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io_result = io_dev_open(nand_dev_con, (uintptr_t)&nand_dev_spec,
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&storage_dev_handle);
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assert(io_result == 0);
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stm32image_dev_info_spec.device_size = nand_dev_spec.device_size;
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idx = IMG_IDX_BL33;
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part = &stm32image_dev_info_spec.part_info[idx];
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part->part_offset = STM32MP_NAND_BL33_OFFSET;
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part->bkp_offset = nand_dev_spec.erase_size;
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#ifdef AARCH32_SP_OPTEE
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idx = IMG_IDX_OPTEE_HEADER;
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part = &stm32image_dev_info_spec.part_info[idx];
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part->part_offset = STM32MP_NAND_TEEH_OFFSET;
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part->bkp_offset = nand_dev_spec.erase_size;
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idx = IMG_IDX_OPTEE_PAGED;
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part = &stm32image_dev_info_spec.part_info[idx];
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part->part_offset = STM32MP_NAND_TEED_OFFSET;
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part->bkp_offset = nand_dev_spec.erase_size;
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idx = IMG_IDX_OPTEE_PAGER;
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part = &stm32image_dev_info_spec.part_info[idx];
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part->part_offset = STM32MP_NAND_TEEX_OFFSET;
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part->bkp_offset = nand_dev_spec.erase_size;
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#endif
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io_result = register_io_dev_stm32image(&stm32image_dev_con);
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assert(io_result == 0);
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io_result = io_dev_open(stm32image_dev_con,
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(uintptr_t)&stm32image_dev_info_spec,
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&image_dev_handle);
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assert(io_result == 0);
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}
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#endif /* STM32MP_RAW_NAND */
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void stm32mp_io_setup(void)
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{
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int io_result __unused;
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@ -346,6 +416,12 @@ void stm32mp_io_setup(void)
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boot_mmc(MMC_IS_EMMC, boot_context->boot_interface_instance);
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break;
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#endif
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#if STM32MP_RAW_NAND
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case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NAND_FMC:
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dmbsy();
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boot_fmc2_nand(boot_context);
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break;
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#endif
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default:
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ERROR("Boot interface %d not supported\n",
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@ -33,6 +33,9 @@
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/* Boot occurred on EMMC */
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#define BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_EMMC 0x2U
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/* Boot occurred on FMC */
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#define BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NAND_FMC 0x3U
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/**
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* @brief Possible value of boot context field 'EmmcXferStatus'
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*/
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@ -51,6 +51,7 @@
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#define MAX_IO_DEVICES U(4)
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#define MAX_IO_HANDLES U(4)
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#define MAX_IO_BLOCK_DEVICES U(1)
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#define MAX_IO_MTD_DEVICES U(1)
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/*******************************************************************************
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* BL2 specific defines.
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@ -0,0 +1,14 @@
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/*
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* Copyright (c) 2019, STMicroelectronics - All Rights Reserved
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef STM32MP1_BOOT_DEVICE_H
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#define STM32MP1_BOOT_DEVICE_H
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#include <drivers/raw_nand.h>
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int plat_get_raw_nand_data(struct rawnand_device *device);
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#endif /* STM32MP1_BOOT_DEVICE_H */
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@ -27,15 +27,18 @@ $(eval $(call add_define,PLAT_PARTITION_MAX_ENTRIES))
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# Boot devices
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STM32MP_EMMC ?= 0
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STM32MP_SDMMC ?= 0
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STM32MP_RAW_NAND ?= 0
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ifeq ($(filter 1,${STM32MP_EMMC} ${STM32MP_SDMMC}),)
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ifeq ($(filter 1,${STM32MP_EMMC} ${STM32MP_SDMMC} ${STM32MP_RAW_NAND}),)
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$(error "No boot device driver is enabled")
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endif
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$(eval $(call assert_boolean,STM32MP_EMMC))
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$(eval $(call assert_boolean,STM32MP_SDMMC))
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$(eval $(call assert_boolean,STM32MP_RAW_NAND))
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$(eval $(call add_define,STM32MP_EMMC))
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$(eval $(call add_define,STM32MP_SDMMC))
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$(eval $(call add_define,STM32MP_RAW_NAND))
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PLAT_INCLUDES := -Iplat/st/common/include/
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PLAT_INCLUDES += -Iplat/st/stm32mp1/include/
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@ -83,6 +86,7 @@ PLAT_BL_COMMON_SOURCES += drivers/arm/tzc/tzc400.c \
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BL2_SOURCES += drivers/io/io_block.c \
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drivers/io/io_dummy.c \
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drivers/io/io_mtd.c \
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drivers/io/io_storage.c \
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drivers/st/crypto/stm32_hash.c \
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drivers/st/io/io_stm32image.c \
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@ -98,6 +102,17 @@ BL2_SOURCES += drivers/mmc/mmc.c \
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drivers/st/mmc/stm32_sdmmc2.c
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endif
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ifeq (${STM32MP_RAW_NAND},1)
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$(eval $(call add_define_val,NAND_ONFI_DETECT,1))
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BL2_SOURCES += drivers/mtd/nand/raw_nand.c \
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drivers/st/fmc/stm32_fmc2_nand.c
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endif
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ifneq ($(filter 1,${STM32MP_RAW_NAND}),)
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BL2_SOURCES += drivers/mtd/nand/core.c \
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plat/st/stm32mp1/stm32mp1_boot_device.c
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endif
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BL2_SOURCES += drivers/st/ddr/stm32mp1_ddr.c \
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drivers/st/ddr/stm32mp1_ram.c
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@ -0,0 +1,125 @@
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/*
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* Copyright (c) 2019, STMicroelectronics - All Rights Reserved
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <errno.h>
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#include <drivers/nand.h>
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#include <lib/utils.h>
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#include <plat/common/platform.h>
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#define SZ_512 0x200U
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#if STM32MP_RAW_NAND
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static int get_data_from_otp(struct nand_device *nand_dev)
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{
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int result;
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uint32_t nand_param;
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/* Check if NAND parameters are stored in OTP */
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result = bsec_shadow_read_otp(&nand_param, NAND_OTP);
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if (result != BSEC_OK) {
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ERROR("BSEC: NAND_OTP Error %i\n", result);
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return -EACCES;
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}
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if (nand_param == 0U) {
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return 0;
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}
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if ((nand_param & NAND_PARAM_STORED_IN_OTP) == 0U) {
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goto ecc;
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}
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/* NAND parameter shall be read from OTP */
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if ((nand_param & NAND_WIDTH_MASK) != 0U) {
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nand_dev->buswidth = NAND_BUS_WIDTH_16;
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} else {
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nand_dev->buswidth = NAND_BUS_WIDTH_8;
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}
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switch ((nand_param & NAND_PAGE_SIZE_MASK) >> NAND_PAGE_SIZE_SHIFT) {
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case NAND_PAGE_SIZE_2K:
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nand_dev->page_size = 0x800U;
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break;
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case NAND_PAGE_SIZE_4K:
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nand_dev->page_size = 0x1000U;
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break;
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case NAND_PAGE_SIZE_8K:
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nand_dev->page_size = 0x2000U;
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break;
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default:
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ERROR("Cannot read NAND page size\n");
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return -EINVAL;
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}
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switch ((nand_param & NAND_BLOCK_SIZE_MASK) >> NAND_BLOCK_SIZE_SHIFT) {
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case NAND_BLOCK_SIZE_64_PAGES:
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nand_dev->block_size = 64U * nand_dev->page_size;
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break;
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case NAND_BLOCK_SIZE_128_PAGES:
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nand_dev->block_size = 128U * nand_dev->page_size;
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break;
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case NAND_BLOCK_SIZE_256_PAGES:
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nand_dev->block_size = 256U * nand_dev->page_size;
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break;
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default:
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ERROR("Cannot read NAND block size\n");
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return -EINVAL;
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}
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nand_dev->size = ((nand_param & NAND_BLOCK_NB_MASK) >>
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NAND_BLOCK_NB_SHIFT) *
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NAND_BLOCK_NB_UNIT * nand_dev->block_size;
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ecc:
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switch ((nand_param & NAND_ECC_BIT_NB_MASK) >>
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NAND_ECC_BIT_NB_SHIFT) {
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case NAND_ECC_BIT_NB_1_BITS:
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nand_dev->ecc.max_bit_corr = 1U;
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break;
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case NAND_ECC_BIT_NB_4_BITS:
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nand_dev->ecc.max_bit_corr = 4U;
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break;
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case NAND_ECC_BIT_NB_8_BITS:
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nand_dev->ecc.max_bit_corr = 8U;
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break;
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case NAND_ECC_ON_DIE:
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nand_dev->ecc.mode = NAND_ECC_ONDIE;
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break;
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default:
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if (nand_dev->ecc.max_bit_corr == 0U) {
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ERROR("No valid eccbit number\n");
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return -EINVAL;
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}
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}
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VERBOSE("OTP: Block %i Page %i Size %lli\n", nand_dev->block_size,
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nand_dev->page_size, nand_dev->size);
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return 0;
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}
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#endif
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#if STM32MP_RAW_NAND
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int plat_get_raw_nand_data(struct rawnand_device *device)
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{
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device->nand_dev->ecc.mode = NAND_ECC_HW;
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device->nand_dev->ecc.size = SZ_512;
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return get_data_from_otp(device->nand_dev);
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}
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#endif
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@ -23,6 +23,7 @@
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#include <stm32mp_common.h>
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#include <stm32mp_dt.h>
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#include <stm32mp_shres_helpers.h>
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#include <stm32mp1_boot_device.h>
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#include <stm32mp1_dbgmcu.h>
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#include <stm32mp1_private.h>
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#endif
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@ -107,15 +108,15 @@ enum ddr_type {
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#ifdef AARCH32_SP_OPTEE
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#if STACK_PROTECTOR_ENABLED
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#define STM32MP_BL2_SIZE U(0x00019000) /* 100 KB for BL2 */
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#define STM32MP_BL2_SIZE U(0x0001A000) /* 100 KB for BL2 */
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#else
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#define STM32MP_BL2_SIZE U(0x00017000) /* 92 KB for BL2 */
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#define STM32MP_BL2_SIZE U(0x00018000) /* 92 KB for BL2 */
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#endif
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#else
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#if STACK_PROTECTOR_ENABLED
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#define STM32MP_BL2_SIZE U(0x00018000) /* 96 KB for BL2 */
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#define STM32MP_BL2_SIZE U(0x00019000) /* 96 KB for BL2 */
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#else
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#define STM32MP_BL2_SIZE U(0x00016000) /* 88 KB for BL2 */
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#define STM32MP_BL2_SIZE U(0x00017000) /* 88 KB for BL2 */
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#endif
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#endif
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@ -144,6 +145,19 @@ enum ddr_type {
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#define STM32MP_BL33_BASE (STM32MP_DDR_BASE + U(0x100000))
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/* Define maximum page size for NAND devices */
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#define PLATFORM_MTD_MAX_PAGE_SIZE U(0x1000)
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/*******************************************************************************
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* STM32MP1 RAW partition offset for MTD devices
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******************************************************************************/
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#define STM32MP_NAND_BL33_OFFSET U(0x00200000)
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#ifdef AARCH32_SP_OPTEE
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#define STM32MP_NAND_TEEH_OFFSET U(0x00600000)
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#define STM32MP_NAND_TEED_OFFSET U(0x00680000)
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#define STM32MP_NAND_TEEX_OFFSET U(0x00700000)
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#endif
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/*******************************************************************************
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* STM32MP1 device/io map related constants (used for MMU)
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******************************************************************************/
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@ -266,6 +280,7 @@ enum ddr_type {
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/* OTP offsets */
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#define DATA0_OTP U(0)
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#define PART_NUMBER_OTP U(1)
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#define NAND_OTP U(9)
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#define PACKAGE_OTP U(16)
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#define HW2_OTP U(18)
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@ -289,6 +304,42 @@ enum ddr_type {
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/* HW2 OTP */
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#define HW2_OTP_PRODUCT_BELOW_2V5 BIT(13)
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/* NAND OTP */
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/* NAND parameter storage flag */
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#define NAND_PARAM_STORED_IN_OTP BIT(31)
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/* NAND page size in bytes */
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#define NAND_PAGE_SIZE_MASK GENMASK_32(30, 29)
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#define NAND_PAGE_SIZE_SHIFT 29
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#define NAND_PAGE_SIZE_2K U(0)
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#define NAND_PAGE_SIZE_4K U(1)
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#define NAND_PAGE_SIZE_8K U(2)
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/* NAND block size in pages */
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#define NAND_BLOCK_SIZE_MASK GENMASK_32(28, 27)
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#define NAND_BLOCK_SIZE_SHIFT 27
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#define NAND_BLOCK_SIZE_64_PAGES U(0)
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#define NAND_BLOCK_SIZE_128_PAGES U(1)
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#define NAND_BLOCK_SIZE_256_PAGES U(2)
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/* NAND number of block (in unit of 256 blocs) */
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#define NAND_BLOCK_NB_MASK GENMASK_32(26, 19)
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#define NAND_BLOCK_NB_SHIFT 19
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#define NAND_BLOCK_NB_UNIT U(256)
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/* NAND bus width in bits */
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#define NAND_WIDTH_MASK BIT(18)
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#define NAND_WIDTH_SHIFT 18
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/* NAND number of ECC bits per 512 bytes */
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#define NAND_ECC_BIT_NB_MASK GENMASK_32(17, 15)
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#define NAND_ECC_BIT_NB_SHIFT 15
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#define NAND_ECC_BIT_NB_UNSET U(0)
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#define NAND_ECC_BIT_NB_1_BITS U(1)
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#define NAND_ECC_BIT_NB_4_BITS U(2)
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#define NAND_ECC_BIT_NB_8_BITS U(3)
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#define NAND_ECC_ON_DIE U(4)
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/*******************************************************************************
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* STM32MP1 TAMP
|
||||
******************************************************************************/
|
||||
|
|
|
|||
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Reference in New Issue