doc: Add missing CVE links to advisories
Some security advisories did not contain a direct link to the CVE page on mitre.org. Change-Id: I80f8f27a25da3a76b564a3e49cafe5e253379f37 Signed-off-by: Paul Beesley <paul.beesley@arm.com>
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Paul Beesley
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@ -2,7 +2,7 @@
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| Title | Malformed Firmware Update SMC can result in copy of |
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| | unexpectedly large data into secure memory |
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+================+=============================================================+
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| CVE ID | CVE-2016-10319 |
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| CVE ID | `CVE-2016-10319`_ |
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+----------------+-------------------------------------------------------------+
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| Date | 18 Oct 2016 |
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+----------------+-------------------------------------------------------------+
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@ -154,5 +154,6 @@ ARM platform version of this function contains a similar vulnerability:
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return success. Platforms that copy this insecure pattern will have the same
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vulnerability.
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.. _CVE-2016-10319: http://cve.mitre.org/cgi-bin/cvename.cgi?name=CVE-2016-10319
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.. _48bfb88: https://github.com/ARM-software/arm-trusted-firmware/commit/48bfb88
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.. _Pull Request #783: https://github.com/ARM-software/arm-trusted-firmware/pull/783
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@ -2,7 +2,7 @@
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| Title | Enabled secure self-hosted invasive debug interface can |
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| | allow normal world to panic secure world |
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+================+=============================================================+
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| CVE ID | CVE-2017-7564 |
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| CVE ID | `CVE-2017-7564`_ |
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+----------------+-------------------------------------------------------------+
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| Date | 02 Feb 2017 |
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+----------------+-------------------------------------------------------------+
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@ -51,6 +51,7 @@ image or integrate the `AArch32 equivalent`_ of the ``el3_arch_init_common``
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macro. Here the affected bits are ``SDCR.SPD``, which should also be assigned to
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``10`` instead of ``00``
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.. _CVE-2017-7564: http://cve.mitre.org/cgi-bin/cvename.cgi?name=CVE-2017-7564
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.. _commit 495f3d3: https://github.com/ARM-software/arm-trusted-firmware/commit/495f3d3
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.. _AArch64 macro: https://github.com/ARM-software/arm-trusted-firmware/blob/bcc2bf0/include/common/aarch64/el3_common_macros.S#L85
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.. _AArch32 equivalent: https://github.com/ARM-software/arm-trusted-firmware/blob/bcc2bf0/include/common/aarch32/el3_common_macros.S#L41
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@ -1,7 +1,7 @@
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+----------------+-------------------------------------------------------------+
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| Title | RO memory is always executable at AArch64 Secure EL1 |
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+================+=============================================================+
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| CVE ID | CVE-2017-7563 |
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| CVE ID | `CVE-2017-7563`_ |
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+----------------+-------------------------------------------------------------+
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| Date | 06 Apr 2017 |
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+----------------+-------------------------------------------------------------+
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@ -78,5 +78,6 @@ The vulnerability is mitigated by the following factors:
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mapped into the secure world is non-executable by setting the ``SCR_EL3.SIF``
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bit. See the ``el3_arch_init_common`` macro in ``el3_common_macros.S``.
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.. _CVE-2017-7563: http://cve.mitre.org/cgi-bin/cvename.cgi?name=CVE-2017-7563
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.. _Pull Request #662: https://github.com/ARM-software/arm-trusted-firmware/pull/662
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.. _Pull Request #924: https://github.com/ARM-software/arm-trusted-firmware/pull/924
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@ -3,7 +3,7 @@
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| | authentication of unexpected data in secure memory in |
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| | AArch32 state |
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+================+=============================================================+
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| CVE ID | CVE-2017-9607 |
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| CVE ID | `CVE-2017-9607`_ |
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+----------------+-------------------------------------------------------------+
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| Date | 20 Jun 2017 |
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+----------------+-------------------------------------------------------------+
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@ -114,6 +114,7 @@ The vulnerability is known to affect all ARM standard platforms when enabling
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the ``TRUSTED_BOARD_BOOT`` and ``ARCH=aarch32`` build options. Other platforms
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may also be affected if they fulfil the above conditions.
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.. _CVE-2017-9607: http://cve.mitre.org/cgi-bin/cvename.cgi?name=CVE-2017-9607
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.. _commit c396b73: https://github.com/ARM-software/arm-trusted-firmware/commit/c396b73
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.. _Pull Request #678: https://github.com/ARM-software/arm-trusted-firmware/pull/678
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.. _Pull Request #939: https://github.com/ARM-software/arm-trusted-firmware/pull/939
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@ -2,7 +2,7 @@
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| Title | Not initializing or saving/restoring ``PMCR_EL0`` can leak |
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| | secure world timing information |
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+================+=============================================================+
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| CVE ID | CVE-2017-15031 |
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| CVE ID | `CVE-2017-15031`_ |
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+----------------+-------------------------------------------------------------+
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| Date | 02 Oct 2017 |
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+----------------+-------------------------------------------------------------+
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@ -39,4 +39,5 @@ sensible default values in the secure context.
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The same issue exists for the equivalent AArch32 register, ``PMCR``, except that
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here ``PMCR_EL0.DP`` architecturally resets to zero.
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.. _CVE-2017-15031: http://cve.mitre.org/cgi-bin/cvename.cgi?name=CVE-2017-15031
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.. _Pull Request #1127: https://github.com/ARM-software/arm-trusted-firmware/pull/1127
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@ -2,7 +2,7 @@
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| Title | Not saving x0 to x3 registers can leak information from one |
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| | Normal World SMC client to another |
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+================+=============================================================+
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| CVE ID | CVE-2018-19440 |
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| CVE ID | `CVE-2018-19440`_ |
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+----------------+-------------------------------------------------------------+
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| Date | 27 Nov 2018 |
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+----------------+-------------------------------------------------------------+
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@ -94,6 +94,7 @@ line 19 (referring to the version of the code as of `commit c385955`_):
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/* Save r0 - r12 in the SMC context */
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stm sp, {r0-r12}
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.. _CVE-2018-19440: http://cve.mitre.org/cgi-bin/cvename.cgi?name=CVE-2018-19440
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.. _commit c385955: https://github.com/ARM-software/arm-trusted-firmware/commit/c385955
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.. _SMC Calling Convention: http://arminfo.emea.arm.com/help/topic/com.arm.doc.den0028b/ARM_DEN0028B_SMC_Calling_Convention.pdf
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.. _Pull Request #1710: https://github.com/ARM-software/arm-trusted-firmware/pull/1710
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