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TF-A GICv2 driver: Introduce makefile 

This patch moves all GICv2 driver files into new added
'gicv2.mk' makefile for the benefit of the generic driver
which can evolve in the future without affecting platforms.

NOTE: Usage of 'drivers/arm/gic/common/gic_common.c' file
is now deprecated and platforms with GICv2 driver need to
be modified to include 'drivers/arm/gic/v2/gicv2.mk' in
their makefiles.

Change-Id: Ib10e71bdda0e5c7e80a049ddce2de1dd839602d1
Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
This commit is contained in:
Alexei Fedorov 2020-07-14 10:47:25 +01:00
parent 70501930dd
commit 1322dc94f7
9 changed files with 383 additions and 24 deletions
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4
drivers/arm/gic/common/gic_common.c
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@ -1,9 +1,11 @@
/*
* Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#pragma message __FILE__ " is deprecated, use gicv2.mk instead"
#include <assert.h>
#include <drivers/arm/gic_common.h>

340
drivers/arm/gic/v2/gicdv2_helpers.c Normal file
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@ -0,0 +1,340 @@
/*
* Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <assert.h>
#include <drivers/arm/gic_common.h>
#include <lib/mmio.h>
#include "../common/gic_common_private.h"
/*******************************************************************************
* GIC Distributor interface accessors for reading entire registers
******************************************************************************/
/*
* Accessor to read the GIC Distributor IGROUPR corresponding to the interrupt
* `id`, 32 interrupt ids at a time.
*/
unsigned int gicd_read_igroupr(uintptr_t base, unsigned int id)
{
unsigned int n = id >> IGROUPR_SHIFT;
return mmio_read_32(base + GICD_IGROUPR + (n << 2));
}
/*
* Accessor to read the GIC Distributor ISENABLER corresponding to the
* interrupt `id`, 32 interrupt ids at a time.
*/
unsigned int gicd_read_isenabler(uintptr_t base, unsigned int id)
{
unsigned int n = id >> ISENABLER_SHIFT;
return mmio_read_32(base + GICD_ISENABLER + (n << 2));
}
/*
* Accessor to read the GIC Distributor ICENABLER corresponding to the
* interrupt `id`, 32 interrupt IDs at a time.
*/
unsigned int gicd_read_icenabler(uintptr_t base, unsigned int id)
{
unsigned int n = id >> ICENABLER_SHIFT;
return mmio_read_32(base + GICD_ICENABLER + (n << 2));
}
/*
* Accessor to read the GIC Distributor ISPENDR corresponding to the
* interrupt `id`, 32 interrupt IDs at a time.
*/
unsigned int gicd_read_ispendr(uintptr_t base, unsigned int id)
{
unsigned int n = id >> ISPENDR_SHIFT;
return mmio_read_32(base + GICD_ISPENDR + (n << 2));
}
/*
* Accessor to read the GIC Distributor ICPENDR corresponding to the
* interrupt `id`, 32 interrupt IDs at a time.
*/
unsigned int gicd_read_icpendr(uintptr_t base, unsigned int id)
{
unsigned int n = id >> ICPENDR_SHIFT;
return mmio_read_32(base + GICD_ICPENDR + (n << 2));
}
/*
* Accessor to read the GIC Distributor ISACTIVER corresponding to the
* interrupt `id`, 32 interrupt IDs at a time.
*/
unsigned int gicd_read_isactiver(uintptr_t base, unsigned int id)
{
unsigned int n = id >> ISACTIVER_SHIFT;
return mmio_read_32(base + GICD_ISACTIVER + (n << 2));
}
/*
* Accessor to read the GIC Distributor ICACTIVER corresponding to the
* interrupt `id`, 32 interrupt IDs at a time.
*/
unsigned int gicd_read_icactiver(uintptr_t base, unsigned int id)
{
unsigned int n = id >> ICACTIVER_SHIFT;
return mmio_read_32(base + GICD_ICACTIVER + (n << 2));
}
/*
* Accessor to read the GIC Distributor IPRIORITYR corresponding to the
* interrupt `id`, 4 interrupt IDs at a time.
*/
unsigned int gicd_read_ipriorityr(uintptr_t base, unsigned int id)
{
unsigned int n = id >> IPRIORITYR_SHIFT;
return mmio_read_32(base + GICD_IPRIORITYR + (n << 2));
}
/*
* Accessor to read the GIC Distributor ICGFR corresponding to the
* interrupt `id`, 16 interrupt IDs at a time.
*/
unsigned int gicd_read_icfgr(uintptr_t base, unsigned int id)
{
unsigned int n = id >> ICFGR_SHIFT;
return mmio_read_32(base + GICD_ICFGR + (n << 2));
}
/*
* Accessor to read the GIC Distributor NSACR corresponding to the
* interrupt `id`, 16 interrupt IDs at a time.
*/
unsigned int gicd_read_nsacr(uintptr_t base, unsigned int id)
{
unsigned int n = id >> NSACR_SHIFT;
return mmio_read_32(base + GICD_NSACR + (n << 2));
}
/*******************************************************************************
* GIC Distributor interface accessors for writing entire registers
******************************************************************************/
/*
* Accessor to write the GIC Distributor IGROUPR corresponding to the
* interrupt `id`, 32 interrupt IDs at a time.
*/
void gicd_write_igroupr(uintptr_t base, unsigned int id, unsigned int val)
{
unsigned int n = id >> IGROUPR_SHIFT;
mmio_write_32(base + GICD_IGROUPR + (n << 2), val);
}
/*
* Accessor to write the GIC Distributor ISENABLER corresponding to the
* interrupt `id`, 32 interrupt IDs at a time.
*/
void gicd_write_isenabler(uintptr_t base, unsigned int id, unsigned int val)
{
unsigned int n = id >> ISENABLER_SHIFT;
mmio_write_32(base + GICD_ISENABLER + (n << 2), val);
}
/*
* Accessor to write the GIC Distributor ICENABLER corresponding to the
* interrupt `id`, 32 interrupt IDs at a time.
*/
void gicd_write_icenabler(uintptr_t base, unsigned int id, unsigned int val)
{
unsigned int n = id >> ICENABLER_SHIFT;
mmio_write_32(base + GICD_ICENABLER + (n << 2), val);
}
/*
* Accessor to write the GIC Distributor ISPENDR corresponding to the
* interrupt `id`, 32 interrupt IDs at a time.
*/
void gicd_write_ispendr(uintptr_t base, unsigned int id, unsigned int val)
{
unsigned int n = id >> ISPENDR_SHIFT;
mmio_write_32(base + GICD_ISPENDR + (n << 2), val);
}
/*
* Accessor to write the GIC Distributor ICPENDR corresponding to the
* interrupt `id`, 32 interrupt IDs at a time.
*/
void gicd_write_icpendr(uintptr_t base, unsigned int id, unsigned int val)
{
unsigned int n = id >> ICPENDR_SHIFT;
mmio_write_32(base + GICD_ICPENDR + (n << 2), val);
}
/*
* Accessor to write the GIC Distributor ISACTIVER corresponding to the
* interrupt `id`, 32 interrupt IDs at a time.
*/
void gicd_write_isactiver(uintptr_t base, unsigned int id, unsigned int val)
{
unsigned int n = id >> ISACTIVER_SHIFT;
mmio_write_32(base + GICD_ISACTIVER + (n << 2), val);
}
/*
* Accessor to write the GIC Distributor ICACTIVER corresponding to the
* interrupt `id`, 32 interrupt IDs at a time.
*/
void gicd_write_icactiver(uintptr_t base, unsigned int id, unsigned int val)
{
unsigned int n = id >> ICACTIVER_SHIFT;
mmio_write_32(base + GICD_ICACTIVER + (n << 2), val);
}
/*
* Accessor to write the GIC Distributor IPRIORITYR corresponding to the
* interrupt `id`, 4 interrupt IDs at a time.
*/
void gicd_write_ipriorityr(uintptr_t base, unsigned int id, unsigned int val)
{
unsigned int n = id >> IPRIORITYR_SHIFT;
mmio_write_32(base + GICD_IPRIORITYR + (n << 2), val);
}
/*
* Accessor to write the GIC Distributor ICFGR corresponding to the
* interrupt `id`, 16 interrupt IDs at a time.
*/
void gicd_write_icfgr(uintptr_t base, unsigned int id, unsigned int val)
{
unsigned int n = id >> ICFGR_SHIFT;
mmio_write_32(base + GICD_ICFGR + (n << 2), val);
}
/*
* Accessor to write the GIC Distributor NSACR corresponding to the
* interrupt `id`, 16 interrupt IDs at a time.
*/
void gicd_write_nsacr(uintptr_t base, unsigned int id, unsigned int val)
{
unsigned int n = id >> NSACR_SHIFT;
mmio_write_32(base + GICD_NSACR + (n << 2), val);
}
/*******************************************************************************
* GIC Distributor functions for accessing the GIC registers
* corresponding to a single interrupt ID. These functions use bitwise
* operations or appropriate register accesses to modify or return
* the bit-field corresponding the single interrupt ID.
******************************************************************************/
unsigned int gicd_get_igroupr(uintptr_t base, unsigned int id)
{
unsigned int bit_num = id & ((1U << IGROUPR_SHIFT) - 1U);
unsigned int reg_val = gicd_read_igroupr(base, id);
return (reg_val >> bit_num) & 0x1U;
}
void gicd_set_igroupr(uintptr_t base, unsigned int id)
{
unsigned int bit_num = id & ((1U << IGROUPR_SHIFT) - 1U);
unsigned int reg_val = gicd_read_igroupr(base, id);
gicd_write_igroupr(base, id, reg_val | (1U << bit_num));
}
void gicd_clr_igroupr(uintptr_t base, unsigned int id)
{
unsigned int bit_num = id & ((1U << IGROUPR_SHIFT) - 1U);
unsigned int reg_val = gicd_read_igroupr(base, id);
gicd_write_igroupr(base, id, reg_val & ~(1U << bit_num));
}
void gicd_set_isenabler(uintptr_t base, unsigned int id)
{
unsigned int bit_num = id & ((1U << ISENABLER_SHIFT) - 1U);
gicd_write_isenabler(base, id, (1U << bit_num));
}
void gicd_set_icenabler(uintptr_t base, unsigned int id)
{
unsigned int bit_num = id & ((1U << ICENABLER_SHIFT) - 1U);
gicd_write_icenabler(base, id, (1U << bit_num));
}
void gicd_set_ispendr(uintptr_t base, unsigned int id)
{
unsigned int bit_num = id & ((1U << ISPENDR_SHIFT) - 1U);
gicd_write_ispendr(base, id, (1U << bit_num));
}
void gicd_set_icpendr(uintptr_t base, unsigned int id)
{
unsigned int bit_num = id & ((1U << ICPENDR_SHIFT) - 1U);
gicd_write_icpendr(base, id, (1U << bit_num));
}
unsigned int gicd_get_isactiver(uintptr_t base, unsigned int id)
{
unsigned int bit_num = id & ((1U << ISACTIVER_SHIFT) - 1U);
unsigned int reg_val = gicd_read_isactiver(base, id);
return (reg_val >> bit_num) & 0x1U;
}
void gicd_set_isactiver(uintptr_t base, unsigned int id)
{
unsigned int bit_num = id & ((1U << ISACTIVER_SHIFT) - 1U);
gicd_write_isactiver(base, id, (1U << bit_num));
}
void gicd_set_icactiver(uintptr_t base, unsigned int id)
{
unsigned int bit_num = id & ((1U << ICACTIVER_SHIFT) - 1U);
gicd_write_icactiver(base, id, (1U << bit_num));
}
void gicd_set_ipriorityr(uintptr_t base, unsigned int id, unsigned int pri)
{
uint8_t val = pri & GIC_PRI_MASK;
mmio_write_8(base + GICD_IPRIORITYR + id, val);
}
void gicd_set_icfgr(uintptr_t base, unsigned int id, unsigned int cfg)
{
/* Interrupt configuration is a 2-bit field */
unsigned int bit_num = id & ((1U << ICFGR_SHIFT) - 1U);
unsigned int bit_shift = bit_num << 1;
uint32_t reg_val = gicd_read_icfgr(base, id);
/* Clear the field, and insert required configuration */
reg_val &= ~(GIC_CFG_MASK << bit_shift);
reg_val |= ((cfg & GIC_CFG_MASK) << bit_shift);
gicd_write_icfgr(base, id, reg_val);
}

15
drivers/arm/gic/v2/gicv2.mk Normal file
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@ -0,0 +1,15 @@
#
# Copyright (c) 2020, Arm Limited. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
# No support for extended PPI and SPI range
GIC_EXT_INTID := 0
GICV2_SOURCES += drivers/arm/gic/v2/gicv2_main.c \
drivers/arm/gic/v2/gicv2_helpers.c \
drivers/arm/gic/v2/gicdv2_helpers.c
# Set GICv2 build option
$(eval $(call add_define,GIC_EXT_INTID))

7
plat/arm/board/a5ds/platform.mk
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@ -14,9 +14,10 @@ DYN_CFG_SOURCES += plat/arm/common/arm_dyn_cfg.c \
plat/arm/common/arm_dyn_cfg_helpers.c \
common/fdt_wrappers.c
A5DS_GIC_SOURCES := drivers/arm/gic/common/gic_common.c \
drivers/arm/gic/v2/gicv2_main.c \
drivers/arm/gic/v2/gicv2_helpers.c \
# Include GICv2 driver files
include drivers/arm/gic/v2/gicv2.mk
A5DS_GIC_SOURCES := ${GICV2_SOURCES} \
plat/common/plat_gicv2.c \
plat/arm/common/arm_gicv2.c

7
plat/arm/board/corstone700/platform.mk
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@ -25,9 +25,10 @@ PLAT_INCLUDES := -Iplat/arm/board/corstone700/common/include \
NEED_BL32 := yes
CORSTONE700_GIC_SOURCES := drivers/arm/gic/common/gic_common.c \
drivers/arm/gic/v2/gicv2_main.c \
drivers/arm/gic/v2/gicv2_helpers.c \
# Include GICv2 driver files
include drivers/arm/gic/v2/gicv2.mk
CORSTONE700_GIC_SOURCES := ${GICV2_SOURCES} \
plat/common/plat_gicv2.c \
plat/arm/common/arm_gicv2.c

9
plat/arm/board/fvp/platform.mk
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@ -72,13 +72,10 @@ else ifeq (${FVP_USE_GIC_DRIVER}, FVP_GICV2)
GIC_ENABLE_V4_EXTN := 0
$(eval $(call add_define,GIC_ENABLE_V4_EXTN))
# No support for extended PPI and SPI range
GIC_EXT_INTID := 0
$(eval $(call add_define,GIC_EXT_INTID))
# Include GICv2 driver files
include drivers/arm/gic/v2/gicv2.mk
FVP_GIC_SOURCES := drivers/arm/gic/common/gic_common.c \
drivers/arm/gic/v2/gicv2_main.c \
drivers/arm/gic/v2/gicv2_helpers.c \
FVP_GIC_SOURCES := ${GICV2_SOURCES} \
plat/common/plat_gicv2.c \
plat/arm/common/arm_gicv2.c

9
plat/arm/board/fvp_ve/platform.mk
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@ -11,10 +11,11 @@ $(eval $(call add_define,FVP_VE_USE_SP804_TIMER))
BL2_SOURCES += drivers/arm/sp804/sp804_delay_timer.c
endif
FVP_VE_GIC_SOURCES := drivers/arm/gic/common/gic_common.c \
drivers/arm/gic/v2/gicv2_main.c \
drivers/arm/gic/v2/gicv2_helpers.c \
plat/common/plat_gicv2.c \
# Include GICv2 driver files
include drivers/arm/gic/v2/gicv2.mk
FVP_VE_GIC_SOURCES := ${GICV2_SOURCES} \
plat/common/plat_gicv2.c \
plat/arm/common/arm_gicv2.c
FVP_VE_SECURITY_SOURCES := plat/arm/board/fvp_ve/fvp_ve_security.c

7
plat/arm/board/juno/platform.mk
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@ -4,9 +4,10 @@
# SPDX-License-Identifier: BSD-3-Clause
#
JUNO_GIC_SOURCES := drivers/arm/gic/common/gic_common.c \
drivers/arm/gic/v2/gicv2_main.c \
drivers/arm/gic/v2/gicv2_helpers.c \
# Include GICv2 driver files
include drivers/arm/gic/v2/gicv2.mk
JUNO_GIC_SOURCES := ${GICV2_SOURCES} \
plat/common/plat_gicv2.c \
plat/arm/common/arm_gicv2.c

9
plat/nvidia/tegra/common/tegra_common.mk
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@ -1,5 +1,5 @@
#
# Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
# Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved.
# Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
@ -20,9 +20,10 @@ TEGRA_GICv3_SOURCES := $(GICV3_SOURCES) \
plat/common/plat_gicv3.c \
${COMMON_DIR}/tegra_gicv3.c
TEGRA_GICv2_SOURCES := drivers/arm/gic/common/gic_common.c \
drivers/arm/gic/v2/gicv2_main.c \
drivers/arm/gic/v2/gicv2_helpers.c \
# Include GICv2 driver files
include drivers/arm/gic/v2/gicv2.mk
TEGRA_GICv2_SOURCES := ${GICV2_SOURCES} \
plat/common/plat_gicv2.c \
${COMMON_DIR}/tegra_gicv2.c