From 138cde662f99f8659be554810d8b8e2d9b1ba7ac Mon Sep 17 00:00:00 2001 From: Ravi Patel Date: Fri, 15 Mar 2019 18:02:48 +0530 Subject: [PATCH] zynqmp: pm: Add CLK_SET_RATE_PARENT in gem clock node Existing implementation does not allow to change the value of the DIV1 because DIV2 does not have SET_RATE_PARENT flag. This causes DIV1 value to be fixed and only value of DIV2 will be adjusted according to required clock rate. Signed-off-by: Ravi Patel Signed-off-by: Jolly Shah Change-Id: Ic6c4ca091bf0c5dc91ebddf86621c82c705dc87b --- plat/xilinx/zynqmp/pm_service/pm_api_clock.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/plat/xilinx/zynqmp/pm_service/pm_api_clock.c b/plat/xilinx/zynqmp/pm_service/pm_api_clock.c index 0ba8e34bc..6e53bd89d 100644 --- a/plat/xilinx/zynqmp/pm_service/pm_api_clock.c +++ b/plat/xilinx/zynqmp/pm_service/pm_api_clock.c @@ -582,7 +582,8 @@ static struct pm_clock_node gem_ref_ungated_nodes[] = { .type = TYPE_DIV2, .offset = 16, .width = 6, - .clkflags = CLK_SET_RATE_NO_REPARENT | CLK_IS_BASIC, + .clkflags = CLK_SET_RATE_NO_REPARENT | CLK_IS_BASIC | + CLK_SET_RATE_PARENT, .typeflags = CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, .mult = NA_MULT, .div = NA_DIV,