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Merge changes from topic "fix-agilex-initialization" into integration 

* changes:
  plat: intel: Additional instruction required to enable global timer
  plat: intel: Fix CCU initialization for Agilex
  plat: intel: Add FPGAINTF configuration to when configuring pinmux
  plat: intel: set DRVSEL and SMPLSEL for DWMMC
  plat: intel: Fix clock configuration bugs
This commit is contained in:
Manish Pandey 2020-06-08 23:16:08 +00:00 committed by TrustedFirmware Code Review
parent 967a6d162d 811af8b768
commit 141568da9f
10 changed files with 93 additions and 45 deletions
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2
plat/intel/soc/agilex/bl2_plat_setup.c
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@ -15,6 +15,7 @@
#include <drivers/ti/uart/uart_16550.h>
#include <lib/xlat_tables/xlat_tables.h>
#include "agilex_mmc.h"
#include "agilex_clock_manager.h"
#include "agilex_memory_controller.h"
#include "agilex_pinmux.h"
@ -76,6 +77,7 @@ void bl2_el3_early_platform_setup(u_register_t x0, u_register_t x1,
socfpga_emac_init();
init_hard_memory_controller();
mailbox_init();
agx_mmc_init();
if (!intel_mailbox_is_fpga_not_ready())
socfpga_bridges_enable();

1
plat/intel/soc/agilex/include/agilex_clock_manager.h
View File

@ -89,6 +89,7 @@
/* Peripheral PLL Macros */
#define CLKMGR_PERPLL_EN_RESET 0x00000fff
#define CLKMGR_PERPLL_EN_SDMMCCLK BIT(5)
#define CLKMGR_PERPLL_GPIODIV_GPIODBCLK_SET(x) (((x) << 0) & 0x0000ffff)
/* Altera Macros */

7
plat/intel/soc/agilex/include/agilex_mmc.h Normal file
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@ -0,0 +1,7 @@
/*
* Copyright (c) 2020, Intel Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
void agx_mmc_init(void);

1
plat/intel/soc/agilex/platform.mk
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@ -37,6 +37,7 @@ BL2_SOURCES += \
plat/intel/soc/agilex/bl2_plat_setup.c \
plat/intel/soc/agilex/soc/agilex_clock_manager.c \
plat/intel/soc/agilex/soc/agilex_memory_controller.c \
plat/intel/soc/agilex/soc/agilex_mmc.c \
plat/intel/soc/agilex/soc/agilex_pinmux.c \
plat/intel/soc/common/bl2_plat_mem_params_desc.c \
plat/intel/soc/common/socfpga_delay_timer.c \

78
plat/intel/soc/agilex/soc/agilex_clock_manager.c
View File

@ -47,14 +47,14 @@ uint32_t wait_fsm(void)
return 0;
}
uint32_t pll_source_sync_config(uint32_t pll_mem_offset)
uint32_t pll_source_sync_config(uint32_t pll_mem_offset, uint32_t data)
{
uint32_t val = 0;
uint32_t count = 0;
uint32_t req_status = 0;
val = (CLKMGR_MEM_WR | CLKMGR_MEM_REQ |
CLKMGR_MEM_WDAT << CLKMGR_MEM_WDAT_OFFSET | CLKMGR_MEM_ADDR);
(data << CLKMGR_MEM_WDAT_OFFSET) | CLKMGR_MEM_ADDR);
mmio_write_32(pll_mem_offset, val);
do {
@ -89,14 +89,17 @@ uint32_t pll_source_sync_read(uint32_t pll_mem_offset)
rdata = mmio_read_32(pll_mem_offset + 0x4);
INFO("rdata (%x) = %x\n", pll_mem_offset + 0x4, rdata);
return 0;
return rdata;
}
void config_clkmgr_handoff(handoff *hoff_ptr)
{
uint32_t mdiv, mscnt, hscnt;
uint32_t arefclk_div, drefclk_div;
uint32_t drefclk_div, refclk_div, rdata;
/* Set clock maanger into boot mode before running configuration */
mmio_setbits_32(CLKMGR_OFFSET + CLKMGR_CTRL,
CLKMGR_CTRL_BOOTMODE_SET_MSK);
/* Bypass all mainpllgrp's clocks */
mmio_write_32(CLKMGR_MAINPLL + CLKMGR_MAINPLL_BYPASS, 0x7);
wait_fsm();
@ -116,26 +119,24 @@ void config_clkmgr_handoff(handoff *hoff_ptr)
/* Setup main PLL dividers */
mdiv = CLKMGR_PLLM_MDIV(hoff_ptr->main_pll_pllm);
arefclk_div = CLKMGR_PLLGLOB_AREFCLKDIV(
hoff_ptr->main_pll_pllglob);
drefclk_div = CLKMGR_PLLGLOB_DREFCLKDIV(
hoff_ptr->main_pll_pllglob);
refclk_div = CLKMGR_PLLGLOB_REFCLKDIV(
hoff_ptr->main_pll_pllglob);
mscnt = 100 / (mdiv / BIT(drefclk_div));
mscnt = 100 / (mdiv * BIT(drefclk_div));
if (!mscnt)
mscnt = 1;
hscnt = (mdiv * mscnt * BIT(drefclk_div) / arefclk_div) - 4;
hscnt = (mdiv * mscnt * BIT(drefclk_div) / refclk_div) - 4;
mmio_write_32(CLKMGR_MAINPLL + CLKMGR_MAINPLL_PLLGLOB,
hoff_ptr->main_pll_pllglob &
~CLKMGR_PLLGLOB_RST_SET_MSK);
mmio_write_32(CLKMGR_MAINPLL + CLKMGR_MAINPLL_FDBCK,
hoff_ptr->main_pll_fdbck);
mmio_write_32(CLKMGR_MAINPLL + CLKMGR_MAINPLL_VCOCALIB,
CLKMGR_VCOCALIB_HSCNT_SET(hscnt) |
CLKMGR_VCOCALIB_MSCNT_SET(mscnt));
mmio_write_32(CLKMGR_MAINPLL + CLKMGR_MAINPLL_NOCDIV,
hoff_ptr->main_pll_nocdiv);
mmio_write_32(CLKMGR_MAINPLL + CLKMGR_MAINPLL_PLLGLOB,
hoff_ptr->main_pll_pllglob);
mmio_write_32(CLKMGR_MAINPLL + CLKMGR_MAINPLL_FDBCK,
hoff_ptr->main_pll_fdbck);
mmio_write_32(CLKMGR_MAINPLL + CLKMGR_MAINPLL_PLLC0,
hoff_ptr->main_pll_pllc0);
mmio_write_32(CLKMGR_MAINPLL + CLKMGR_MAINPLL_PLLC1,
@ -150,33 +151,33 @@ void config_clkmgr_handoff(handoff *hoff_ptr)
hoff_ptr->main_pll_mpuclk);
mmio_write_32(CLKMGR_MAINPLL + CLKMGR_MAINPLL_NOCCLK,
hoff_ptr->main_pll_nocclk);
mmio_write_32(CLKMGR_MAINPLL + CLKMGR_MAINPLL_NOCDIV,
hoff_ptr->main_pll_nocdiv);
/* Setup peripheral PLL dividers */
mdiv = CLKMGR_PLLM_MDIV(hoff_ptr->per_pll_pllm);
arefclk_div = CLKMGR_PLLGLOB_AREFCLKDIV(
hoff_ptr->per_pll_pllglob);
drefclk_div = CLKMGR_PLLGLOB_DREFCLKDIV(
hoff_ptr->per_pll_pllglob);
refclk_div = CLKMGR_PLLGLOB_REFCLKDIV(
hoff_ptr->per_pll_pllglob);
mscnt = 100 / (mdiv / BIT(drefclk_div));
mscnt = 100 / (mdiv * BIT(drefclk_div));
if (!mscnt)
mscnt = 1;
hscnt = (mdiv * mscnt * BIT(drefclk_div) / arefclk_div) - 4;
hscnt = (mdiv * mscnt * BIT(drefclk_div) / refclk_div) - 4;
mmio_write_32(CLKMGR_PERPLL + CLKMGR_PERPLL_PLLGLOB,
hoff_ptr->per_pll_pllglob &
~CLKMGR_PLLGLOB_RST_SET_MSK);
mmio_write_32(CLKMGR_PERPLL + CLKMGR_PERPLL_FDBCK,
hoff_ptr->per_pll_fdbck);
mmio_write_32(CLKMGR_PERPLL + CLKMGR_PERPLL_VCOCALIB,
CLKMGR_VCOCALIB_HSCNT_SET(hscnt) |
CLKMGR_VCOCALIB_MSCNT_SET(mscnt));
mmio_write_32(CLKMGR_PERPLL + CLKMGR_PERPLL_EMACCTL,
hoff_ptr->per_pll_emacctl);
mmio_write_32(CLKMGR_PERPLL + CLKMGR_PERPLL_GPIODIV,
CLKMGR_PERPLL_GPIODIV_GPIODBCLK_SET(
hoff_ptr->per_pll_gpiodiv));
mmio_write_32(CLKMGR_PERPLL + CLKMGR_PERPLL_PLLGLOB,
hoff_ptr->per_pll_pllglob);
mmio_write_32(CLKMGR_PERPLL + CLKMGR_PERPLL_FDBCK,
hoff_ptr->per_pll_fdbck);
mmio_write_32(CLKMGR_PERPLL + CLKMGR_PERPLL_PLLC0,
hoff_ptr->per_pll_pllc0);
mmio_write_32(CLKMGR_PERPLL + CLKMGR_PERPLL_PLLC1,
@ -187,6 +188,10 @@ void config_clkmgr_handoff(handoff *hoff_ptr)
hoff_ptr->per_pll_pllc3);
mmio_write_32(CLKMGR_PERPLL + CLKMGR_PERPLL_PLLM,
hoff_ptr->per_pll_pllm);
mmio_write_32(CLKMGR_PERPLL + CLKMGR_PERPLL_EMACCTL,
hoff_ptr->per_pll_emacctl);
mmio_write_32(CLKMGR_PERPLL + CLKMGR_PERPLL_GPIODIV,
hoff_ptr->per_pll_gpiodiv);
/* Take both PLL out of reset and power up */
mmio_setbits_32(CLKMGR_MAINPLL + CLKMGR_MAINPLL_PLLGLOB,
@ -196,14 +201,17 @@ void config_clkmgr_handoff(handoff *hoff_ptr)
CLKMGR_PLLGLOB_PD_SET_MSK |
CLKMGR_PLLGLOB_RST_SET_MSK);
rdata = pll_source_sync_read(CLKMGR_MAINPLL +
CLKMGR_MAINPLL_MEM);
pll_source_sync_config(CLKMGR_MAINPLL + CLKMGR_MAINPLL_MEM,
rdata | 0x80);
rdata = pll_source_sync_read(CLKMGR_PERPLL + CLKMGR_PERPLL_MEM);
pll_source_sync_config(CLKMGR_PERPLL + CLKMGR_PERPLL_MEM,
rdata | 0x80);
wait_pll_lock();
pll_source_sync_config(CLKMGR_MAINPLL + CLKMGR_MAINPLL_MEM);
pll_source_sync_read(CLKMGR_MAINPLL + CLKMGR_MAINPLL_MEM);
pll_source_sync_config(CLKMGR_PERPLL + CLKMGR_PERPLL_MEM);
pll_source_sync_read(CLKMGR_PERPLL + CLKMGR_PERPLL_MEM);
/*Configure Ping Pong counters in altera group */
mmio_write_32(CLKMGR_ALTERA + CLKMGR_ALTERA_EMACACTR,
hoff_ptr->alt_emacactr);
@ -241,7 +249,7 @@ void config_clkmgr_handoff(handoff *hoff_ptr)
/* Clear loss lock interrupt status register that */
/* might be set during configuration */
mmio_setbits_32(CLKMGR_OFFSET + CLKMGR_INTRCLR,
mmio_clrbits_32(CLKMGR_OFFSET + CLKMGR_INTRCLR,
CLKMGR_INTRCLR_MAINLOCKLOST_SET_MSK |
CLKMGR_INTRCLR_PERLOCKLOST_SET_MSK);

19
plat/intel/soc/agilex/soc/agilex_mmc.c Normal file
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@ -0,0 +1,19 @@
/*
* Copyright (c) 2020, Intel Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <lib/mmio.h>
#include "socfpga_system_manager.h"
#include "agilex_clock_manager.h"
void agx_mmc_init(void)
{
mmio_clrbits_32(CLKMGR_PERPLL + CLKMGR_PERPLL_EN,
CLKMGR_PERPLL_EN_SDMMCCLK);
mmio_write_32(SOCFPGA_SYSMGR(SDMMC),
SYSMGR_SDMMC_SMPLSEL(0) | SYSMGR_SDMMC_DRVSEL(3));
mmio_setbits_32(CLKMGR_PERPLL + CLKMGR_PERPLL_EN,
CLKMGR_PERPLL_EN_SDMMCCLK);
}

8
plat/intel/soc/agilex/soc/agilex_pinmux.c
View File

@ -7,6 +7,7 @@
#include <lib/mmio.h>
#include "agilex_pinmux.h"
#include "socfpga_system_manager.h"
const uint32_t sysmgr_pinmux_array_sel[] = {
0x00000000, 0x00000001, /* usb */
@ -185,6 +186,12 @@ const uint32_t sysmgr_pinmux_array_iodelay[] = {
0x0000011c, 0x00000000
};
void config_fpgaintf_mod(void)
{
mmio_write_32(SOCFPGA_SYSMGR(FPGAINTF_EN_2), 1<<8);
}
void config_pinmux(handoff *hoff_ptr)
{
unsigned int i;
@ -213,5 +220,6 @@ void config_pinmux(handoff *hoff_ptr)
hoff_ptr->pinmux_iodelay_array[i+1]);
}
config_fpgaintf_mod();
}

15
plat/intel/soc/common/drivers/ccu/ncore_ccu.c
View File

@ -35,14 +35,12 @@ uint32_t directory_init(void)
uint32_t dir, sf, ret;
for (dir = 0; dir < subsystem_id.num_directory; dir++) {
dir_sf_mtn = DIRECTORY_UNIT(dir, NCORE_DIRUSFMCR);
dir_sf_en = DIRECTORY_UNIT(dir, NCORE_DIRUSFER);
for (sf = 0; sf < subsystem_id.num_snoop_filter; sf++) {
dir_sf_mtn = DIRECTORY_UNIT(dir, NCORE_DIRUSFMCR);
dir_sf_en = DIRECTORY_UNIT(dir, NCORE_DIRUSFER);
/* Initialize All Entries */
mmio_write_32(dir_sf_mtn, SNOOP_FILTER_ID(sf));
mmio_write_32(dir_sf_mtn, SNOOP_FILTER_ID(dir));
/* Poll Active Bit */
ret = poll_active_bit(dir);
@ -52,7 +50,7 @@ uint32_t directory_init(void)
}
/* Snoope Filter Enable */
mmio_write_32(dir_sf_en, BIT(sf));
mmio_setbits_32(dir_sf_en, BIT(sf));
}
}
@ -64,11 +62,8 @@ uint32_t coherent_agent_intfc_init(void)
uint32_t dir, ca, ca_id, ca_type, ca_snoop_en;
for (dir = 0; dir < subsystem_id.num_directory; dir++) {
ca_snoop_en = DIRECTORY_UNIT(dir, NCORE_DIRUCASER0);
for (ca = 0; ca < subsystem_id.num_coh_agent; ca++) {
ca_snoop_en = DIRECTORY_UNIT(ca, NCORE_DIRUCASER0);
ca_id = mmio_read_32(COH_AGENT_UNIT(ca, NCORE_CAIUIDR));
/* Coh Agent Snoop Enable */

3
plat/intel/soc/common/include/socfpga_system_manager.h
View File

@ -13,6 +13,8 @@
#define SOCFPGA_SYSMGR_SDMMC 0x28
#define SOCFPGA_SYSMGR_FPGAINTF_EN_2 0x6c
#define SOCFPGA_SYSMGR_EMAC_0 0x44
#define SOCFPGA_SYSMGR_EMAC_1 0x48
#define SOCFPGA_SYSMGR_EMAC_2 0x4c
@ -32,6 +34,7 @@
/* Field Masking */
#define SYSMGR_SDMMC_DRVSEL(x) (((x) & 0x7) << 0)
#define SYSMGR_SDMMC_SMPLSEL(x) (((x) & 0x7) << 4)
#define IDLE_DATA_LWSOC2FPGA BIT(0)
#define IDLE_DATA_SOC2FPGA BIT(4)

4
plat/intel/soc/common/socfpga_delay_timer.c
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@ -36,4 +36,8 @@ void socfpga_delay_timer_init(void)
{
timer_init(&plat_timer_ops);
mmio_write_32(SOCFPGA_GLOBAL_TIMER, SOCFPGA_GLOBAL_TIMER_EN);
asm volatile("msr cntp_ctl_el0, %0" : : "r" (SOCFPGA_GLOBAL_TIMER_EN));
asm volatile("msr cntp_tval_el0, %0" : : "r" (~0));
}