From 1471475516cbf1b4a411d5ef853bd92d0edd542e Mon Sep 17 00:00:00 2001
From: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>
Date: Tue, 7 Dec 2021 17:20:10 +0000
Subject: [PATCH] feat(cpu): add library support for Poseidon CPU

This patch adds the basic CPU library code to support the Poseidon CPU
in TF-A. Poseidon is derived from HunterELP core, an implementation of
v9.2 architecture. Currently, Hunter CPU the predecessor to HunterELP,
is supported in TF-A. Accordingly the Hunter CPU library code has been
as the base and adapted here.

Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>
Change-Id: I406b4de156a67132e6a5523370115aaac933f18d
---
 include/lib/cpus/aarch64/neoverse_poseidon.h | 24 ++++++
 lib/cpus/aarch64/neoverse_poseidon.S         | 77 ++++++++++++++++++++
 plat/arm/board/fvp/platform.mk               |  3 +-
 3 files changed, 103 insertions(+), 1 deletion(-)
 create mode 100644 include/lib/cpus/aarch64/neoverse_poseidon.h
 create mode 100644 lib/cpus/aarch64/neoverse_poseidon.S

diff --git a/include/lib/cpus/aarch64/neoverse_poseidon.h b/include/lib/cpus/aarch64/neoverse_poseidon.h
new file mode 100644
index 000000000..0a8b1d1f7
--- /dev/null
+++ b/include/lib/cpus/aarch64/neoverse_poseidon.h
@@ -0,0 +1,24 @@
+/*
+ * Copyright (c) 2022, ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef NEOVERSE_POSEIDON_H
+#define NEOVERSE_POSEIDON_H
+
+
+#define NEOVERSE_POSEIDON_MIDR                      		U(0x410FD830)
+
+/*******************************************************************************
+ * CPU Extended Control register specific definitions.
+ ******************************************************************************/
+#define NEOVERSE_POSEIDON_CPUECTLR_EL1				S3_0_C15_C1_4
+
+/*******************************************************************************
+ * CPU Power Control register specific definitions
+ ******************************************************************************/
+#define NEOVERSE_POSEIDON_CPUPWRCTLR_EL1			S3_0_C15_C2_7
+#define NEOVERSE_POSEIDON_CPUPWRCTLR_EL1_CORE_PWRDN_BIT		U(1)
+
+#endif /* NEOVERSE_POSEIDON_H */
diff --git a/lib/cpus/aarch64/neoverse_poseidon.S b/lib/cpus/aarch64/neoverse_poseidon.S
new file mode 100644
index 000000000..43a93aa3c
--- /dev/null
+++ b/lib/cpus/aarch64/neoverse_poseidon.S
@@ -0,0 +1,77 @@
+/*
+ * Copyright (c) 2022, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <arch.h>
+#include <asm_macros.S>
+#include <common/bl_common.h>
+#include <neoverse_poseidon.h>
+#include <cpu_macros.S>
+#include <plat_macros.S>
+
+/* Hardware handled coherency */
+#if HW_ASSISTED_COHERENCY == 0
+#error "Neoverse Poseidon must be compiled with HW_ASSISTED_COHERENCY enabled"
+#endif
+
+/* 64-bit only core */
+#if CTX_INCLUDE_AARCH32_REGS == 1
+#error "Neoverse Poseidon supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
+#endif
+
+	/* ---------------------------------------------
+	 * HW will do the cache maintenance while powering down
+	 * ---------------------------------------------
+	 */
+func neoverse_poseidon_core_pwr_dwn
+	/* ---------------------------------------------
+	 * Enable CPU power down bit in power control register
+	 * ---------------------------------------------
+	 */
+	mrs	x0, NEOVERSE_POSEIDON_CPUPWRCTLR_EL1
+	orr	x0, x0, #NEOVERSE_POSEIDON_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
+	msr	NEOVERSE_POSEIDON_CPUPWRCTLR_EL1, x0
+	isb
+	ret
+endfunc neoverse_poseidon_core_pwr_dwn
+
+#if REPORT_ERRATA
+	/*
+	 * Errata printing function for Neoverse Poseidon. Must follow AAPCS.
+	 */
+func neoverse_poseidon_errata_report
+	ret
+endfunc neoverse_poseidon_errata_report
+#endif
+
+func neoverse_poseidon_reset_func
+	/* Disable speculative loads */
+	msr	SSBS, xzr
+	isb
+	ret
+endfunc neoverse_poseidon_reset_func
+
+	/* ---------------------------------------------
+	 * This function provides Neoverse-Poseidon specific
+	 * register information for crash reporting.
+	 * It needs to return with x6 pointing to
+	 * a list of register names in ascii and
+	 * x8 - x15 having values of registers to be
+	 * reported.
+	 * ---------------------------------------------
+	 */
+.section .rodata.neoverse_poseidon_regs, "aS"
+neoverse_poseidon_regs:  /* The ascii list of register names to be reported */
+	.asciz	"cpuectlr_el1", ""
+
+func neoverse_poseidon_cpu_reg_dump
+	adr	x6, neoverse_poseidon_regs
+	mrs	x8, NEOVERSE_POSEIDON_CPUECTLR_EL1
+	ret
+endfunc neoverse_poseidon_cpu_reg_dump
+
+declare_cpu_ops neoverse_poseidon, NEOVERSE_POSEIDON_MIDR, \
+	neoverse_poseidon_reset_func, \
+	neoverse_poseidon_core_pwr_dwn
diff --git a/plat/arm/board/fvp/platform.mk b/plat/arm/board/fvp/platform.mk
index e184c3f2c..a24a2e50c 100644
--- a/plat/arm/board/fvp/platform.mk
+++ b/plat/arm/board/fvp/platform.mk
@@ -143,7 +143,8 @@ else
 					lib/cpus/aarch64/cortex_a78c.S		\
 					lib/cpus/aarch64/cortex_hayes.S		\
 					lib/cpus/aarch64/cortex_hunter.S	\
-					lib/cpus/aarch64/cortex_x2.S
+					lib/cpus/aarch64/cortex_x2.S		\
+					lib/cpus/aarch64/neoverse_poseidon.S
 	endif
 	# AArch64/AArch32 cores
 	FVP_CPU_LIBS	+=	lib/cpus/aarch64/cortex_a55.S		\