Tegra: flowctrl: helper functions to assist with cluster power states
This patch adds helper functions to help platforms with cluster state entry and exit decisions. * tegra_fc_ccplex_pgexit_lock(): lock CPU power ungate * tegra_fc_ccplex_pgexit_unlock(): unlock CPU power ungate * tegra_fc_is_ccx_allowed(): CCx state entry allowed on this CPU? Change-Id: I6490d34bf380dc03ae203eb3028f61984f06931c Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
This commit is contained in:
Varun Wadekar
parent
fdb82faad3
commit
1483d4e0a4
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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@ -15,6 +15,7 @@
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#include <flowctrl.h>
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#include <pmc.h>
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#include <tegra_def.h>
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#include <utils_def.h>
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#define CLK_RST_DEV_L_SET 0x300
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#define CLK_RST_DEV_L_CLR 0x304
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@ -75,6 +76,47 @@ static void tegra_fc_prepare_suspend(int cpu_id, uint32_t csr)
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tegra_fc_cpu_csr(cpu_id, val | csr);
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}
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/*******************************************************************************
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* After this, no core can wake from C7 until the action is reverted.
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* If a wake up event is asserted, the FC state machine will stall until
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* the action is reverted.
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******************************************************************************/
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void tegra_fc_ccplex_pgexit_lock(void)
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{
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unsigned int i, cpu = read_mpidr() & MPIDR_CPU_MASK;
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uint32_t flags = tegra_fc_read_32(FLOWCTRL_FC_SEQ_INTERCEPT) & ~INTERCEPT_IRQ_PENDING;;
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uint32_t icept_cpu_flags[] = {
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INTERCEPT_EXIT_PG_CORE0,
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INTERCEPT_EXIT_PG_CORE1,
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INTERCEPT_EXIT_PG_CORE2,
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INTERCEPT_EXIT_PG_CORE3
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};
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/* set the intercept flags */
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for (i = 0; i < ARRAY_SIZE(icept_cpu_flags); i++) {
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/* skip current CPU */
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if (i == cpu)
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continue;
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/* enable power gate exit intercept locks */
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flags |= icept_cpu_flags[i];
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}
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tegra_fc_write_32(FLOWCTRL_FC_SEQ_INTERCEPT, flags);
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(void)tegra_fc_read_32(FLOWCTRL_FC_SEQ_INTERCEPT);
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}
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/*******************************************************************************
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* Revert the ccplex powergate exit locks
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******************************************************************************/
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void tegra_fc_ccplex_pgexit_unlock(void)
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{
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/* clear lock bits, clear pending interrupts */
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tegra_fc_write_32(FLOWCTRL_FC_SEQ_INTERCEPT, INTERCEPT_IRQ_PENDING);
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(void)tegra_fc_read_32(FLOWCTRL_FC_SEQ_INTERCEPT);
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}
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/*******************************************************************************
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* Powerdn the current CPU
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******************************************************************************/
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@ -128,6 +170,31 @@ void tegra_fc_cluster_powerdn(uint32_t mpidr)
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tegra_fc_prepare_suspend(cpu, val);
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}
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/*******************************************************************************
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* Check if cluster idle or power down state is allowed from this CPU
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******************************************************************************/
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bool tegra_fc_is_ccx_allowed(void)
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{
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unsigned int i, cpu = read_mpidr() & MPIDR_CPU_MASK;
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uint32_t val;
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bool ccx_allowed = true;
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for (i = 0; i < ARRAY_SIZE(flowctrl_offset_cpu_csr); i++) {
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/* skip current CPU */
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if (i == cpu)
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continue;
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/* check if all other CPUs are already halted */
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val = mmio_read_32(flowctrl_offset_cpu_csr[i]);
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if ((val & FLOWCTRL_CSR_HALT_MASK) == 0U) {
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ccx_allowed = false;
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}
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}
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return ccx_allowed;
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}
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/*******************************************************************************
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* Suspend the entire SoC
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******************************************************************************/
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@ -11,7 +11,7 @@
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#include <tegra_def.h>
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#define FLOWCTRL_HALT_CPU0_EVENTS 0x0U
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#define FLOWCTRL_HALT_CPU0_EVENTS (0x0U)
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#define FLOWCTRL_WAITEVENT (2U << 29)
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#define FLOWCTRL_WAIT_FOR_INTERRUPT (4U << 29)
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#define FLOWCTRL_JTAG_RESUME (1U << 28)
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@ -20,21 +20,46 @@
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#define FLOWCTRL_HALT_LIC_FIQ (1U << 10)
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#define FLOWCTRL_HALT_GIC_IRQ (1U << 9)
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#define FLOWCTRL_HALT_GIC_FIQ (1U << 8)
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#define FLOWCTRL_HALT_BPMP_EVENTS 0x4U
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#define FLOWCTRL_CPU0_CSR 0x8U
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#define FLOW_CTRL_CSR_PWR_OFF_STS (1U << 16)
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#define FLOWCTRL_HALT_BPMP_EVENTS (0x4U)
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#define FLOWCTRL_CPU0_CSR (0x8U)
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#define FLOWCTRL_CSR_HALT_MASK (1U << 22)
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#define FLOWCTRL_CSR_PWR_OFF_STS (1U << 16)
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#define FLOWCTRL_CSR_INTR_FLAG (1U << 15)
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#define FLOWCTRL_CSR_EVENT_FLAG (1U << 14)
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#define FLOWCTRL_CSR_IMMEDIATE_WAKE (1U << 3)
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#define FLOWCTRL_CSR_ENABLE (1U << 0)
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#define FLOWCTRL_HALT_CPU1_EVENTS 0x14U
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#define FLOWCTRL_CPU1_CSR 0x18U
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#define FLOW_CTLR_FLOW_DBG_QUAL 0x50U
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#define FLOWCTRL_HALT_CPU1_EVENTS (0x14U)
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#define FLOWCTRL_CPU1_CSR (0x18U)
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#define FLOW_CTLR_FLOW_DBG_QUAL (0x50U)
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#define FLOWCTRL_FIQ2CCPLEX_ENABLE (1U << 28)
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#define FLOWCTRL_CC4_CORE0_CTRL 0x6cU
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#define FLOWCTRL_WAIT_WFI_BITMAP 0x100U
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#define FLOWCTRL_L2_FLUSH_CONTROL 0x94U
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#define FLOWCTRL_BPMP_CLUSTER_CONTROL 0x98U
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#define FLOWCTRL_FC_SEQ_INTERCEPT (0x5cU)
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#define INTERCEPT_IRQ_PENDING (0xffU)
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#define INTERCEPT_HVC (U(1) << 21)
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#define INTERCEPT_ENTRY_CC4 (U(1) << 20)
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#define INTERCEPT_ENTRY_PG_NONCPU (U(1) << 19)
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#define INTERCEPT_EXIT_PG_NONCPU (U(1) << 18)
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#define INTERCEPT_ENTRY_RG_CPU (U(1) << 17)
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#define INTERCEPT_EXIT_RG_CPU (U(1) << 16)
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#define INTERCEPT_ENTRY_PG_CORE0 (U(1) << 15)
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#define INTERCEPT_EXIT_PG_CORE0 (U(1) << 14)
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#define INTERCEPT_ENTRY_PG_CORE1 (U(1) << 13)
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#define INTERCEPT_EXIT_PG_CORE1 (U(1) << 12)
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#define INTERCEPT_ENTRY_PG_CORE2 (U(1) << 11)
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#define INTERCEPT_EXIT_PG_CORE2 (U(1) << 10)
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#define INTERCEPT_ENTRY_PG_CORE3 (U(1) << 9)
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#define INTERCEPT_EXIT_PG_CORE3 (U(1) << 8)
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#define INTERRUPT_PENDING_NONCPU (U(1) << 7)
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#define INTERRUPT_PENDING_CRAIL (U(1) << 6)
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#define INTERRUPT_PENDING_CORE0 (U(1) << 5)
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#define INTERRUPT_PENDING_CORE1 (U(1) << 4)
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#define INTERRUPT_PENDING_CORE2 (U(1) << 3)
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#define INTERRUPT_PENDING_CORE3 (U(1) << 2)
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#define CC4_INTERRUPT_PENDING (U(1) << 1)
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#define HVC_INTERRUPT_PENDING (U(1) << 0)
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#define FLOWCTRL_CC4_CORE0_CTRL (0x6cU)
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#define FLOWCTRL_WAIT_WFI_BITMAP (0x100U)
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#define FLOWCTRL_L2_FLUSH_CONTROL (0x94U)
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#define FLOWCTRL_BPMP_CLUSTER_CONTROL (0x98U)
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#define FLOWCTRL_BPMP_CLUSTER_PWRON_LOCK (1U << 2)
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#define FLOWCTRL_ENABLE_EXT 12U
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@ -52,6 +77,8 @@ static inline void tegra_fc_write_32(uint32_t off, uint32_t val)
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mmio_write_32(TEGRA_FLOWCTRL_BASE + off, val);
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}
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void tegra_fc_ccplex_pgexit_lock(void);
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void tegra_fc_ccplex_pgexit_unlock(void);
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void tegra_fc_cluster_idle(uint32_t midr);
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void tegra_fc_cpu_powerdn(uint32_t mpidr);
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void tegra_fc_cluster_powerdn(uint32_t midr);
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@ -59,6 +86,7 @@ void tegra_fc_cpu_on(int cpu);
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void tegra_fc_cpu_off(int cpu);
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void tegra_fc_disable_fiq_to_ccplex_routing(void);
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void tegra_fc_enable_fiq_to_ccplex_routing(void);
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bool tegra_fc_is_ccx_allowed(void);
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void tegra_fc_lock_active_cluster(void);
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void tegra_fc_reset_bpmp(void);
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void tegra_fc_soc_powerdn(uint32_t midr);
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