Miscellaneous doc fixes for v1.2
Change-Id: I6f49bd779f2a4d577c6443dd160290656cdbc59b
This commit is contained in:
Sandrine Bailleux
Dan Handley
parent
3f61835baf
commit
1645d3ee60
6
Makefile
6
Makefile
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@ -56,7 +56,7 @@ SPD := none
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BASE_COMMIT := origin/master
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# NS timer register save and restore
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NS_TIMER_SWITCH := 0
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# By default, Bl1 acts as the reset handler, not BL31
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# By default, BL1 acts as the reset handler, not BL31
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RESET_TO_BL31 := 0
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# Include FP registers in cpu context
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CTX_INCLUDE_FPREGS := 0
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@ -295,7 +295,7 @@ include plat/compat/plat_compat.mk
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endif
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# Include the CPU specific operations makefile. By default all CPU errata
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# workarounds and CPU specifc optimisations are disabled. This can be
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# workarounds and CPU specific optimisations are disabled. This can be
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# overridden by the platform.
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include lib/cpus/cpu-ops.mk
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@ -309,7 +309,7 @@ ifeq (${DISABLE_PEDANTIC},0)
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CFLAGS += -pedantic
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endif
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# Using the ARM Trusted Firmware BL2 implies that a BL33 image also need to be
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# Using the ARM Trusted Firmware BL2 implies that a BL33 image also needs to be
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# supplied for the FIP and Certificate generation tools. This flag can be
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# overridden by the platform.
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ifdef BL2_SOURCES
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@ -359,7 +359,7 @@ func report_unhandled_exception
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report_unhandled_interrupt:
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b crash_panic
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endfunc report_unhandled_exception
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#endif /* CRASH_REPORING */
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#endif /* CRASH_REPORTING */
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func crash_panic
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@ -61,7 +61,7 @@ endif
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BL31_LINKERFILE := bl31/bl31.ld.S
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# Flag used to inidicate if Crash reporting via console should be included
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# Flag used to indicate if Crash reporting via console should be included
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# in BL31. This defaults to being present in DEBUG builds only
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ifndef CRASH_REPORTING
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CRASH_REPORTING := $(DEBUG)
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@ -110,7 +110,7 @@ void runtime_svc_init(void)
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}
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/*
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* The runtime service may have seperate rt_svc_desc_t
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* The runtime service may have separate rt_svc_desc_t
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* for its fast smc and standard smc. Since the service itself
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* need to be initialized only once, only one of them will have
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* an initialisation routine defined. Call the initialisation
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@ -303,7 +303,7 @@ func fpregs_context_restore
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/*
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* No explict ISB required here as ERET to
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* swtich to secure EL1 or non-secure world
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* switch to secure EL1 or non-secure world
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* covers it
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*/
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@ -99,8 +99,8 @@ The functionality implemented by this stage is as follows.
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Whenever a CPU is released from reset, BL1 needs to distinguish between a warm
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boot and a cold boot. This is done using platform-specific mechanisms (see the
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`platform_get_entrypoint()` function in the [Porting Guide]). In the case of a
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warm boot, a CPU is expected to continue execution from a seperate
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`plat_get_my_entrypoint()` function in the [Porting Guide]). In the case of a
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warm boot, a CPU is expected to continue execution from a separate
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entrypoint. In the case of a cold boot, the secondary CPUs are placed in a safe
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platform-specific state (see the `plat_secondary_cold_boot_setup()` function in
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the [Porting Guide]) while the primary CPU executes the remaining cold boot path
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@ -217,7 +217,7 @@ In the normal boot flow, BL1 execution continues as follows:
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there is not enough free trusted SRAM the following error message is
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printed:
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"Failed to load boot loader stage 2 (BL2) firmware."
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"Failed to load BL2 firmware."
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If the load is successful, BL1 updates the limits of the remaining free
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trusted SRAM. It also populates information about the amount of trusted
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@ -228,7 +228,7 @@ In the normal boot flow, BL1 execution continues as follows:
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2. BL1 prints the following string from the primary CPU to indicate successful
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execution of the BL1 stage:
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"Booting trusted firmware boot loader stage 1"
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"Booting Trusted Firmware"
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3. BL1 passes control to the BL2 image at Secure EL1, starting from its load
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address.
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@ -712,7 +712,7 @@ required support.
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| PSCI v1.0 API |Supported| Comments |
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|:----------------------|:--------|:------------------------------------------|
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|`PSCI_VERSION` | Yes | The version returned is 1.0 |
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|`CPU_SUSPEND` | Yes* | The original `power_state` format is used |
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|`CPU_SUSPEND` | Yes* | |
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|`CPU_OFF` | Yes* | |
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|`CPU_ON` | Yes* | |
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|`AFFINITY_INFO` | Yes | |
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@ -796,7 +796,7 @@ To do this the SPD has to register a BL32 initialization function during
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initialization of the SPD service. The BL32 initialization function has this
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prototype:
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int32_t init();
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int32_t init(void);
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and is registered using the `bl31_register_bl32_init()` function.
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@ -806,7 +806,7 @@ before returning through EL3 and running the non-trusted firmware (BL33):
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1. In the BL32 setup function, use `bl31_set_next_image_type()` to
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request that the exit from `bl31_main()` is to the BL32 entrypoint in
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Secure-EL1. BL31 will exit to BL32 using the asynchronous method by
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calling bl31_prepare_next_image_entry() and el3_exit().
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calling `bl31_prepare_next_image_entry()` and `el3_exit()`.
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When the BL32 has completed initialization at Secure-EL1, it returns to
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BL31 by issuing an SMC, using a Function ID allocated to the SPD. On
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@ -816,7 +816,7 @@ before returning through EL3 and running the non-trusted firmware (BL33):
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the normal world firmware BL33. On return from the handler the framework
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will exit to EL2 and run BL33.
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2. The BL32 setup function registers a initialization function using
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2. The BL32 setup function registers an initialization function using
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`bl31_register_bl32_init()` which provides a SPD-defined mechanism to
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invoke a 'world-switch synchronous call' to Secure-EL1 to run the BL32
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entrypoint.
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@ -1501,7 +1501,7 @@ structure is allocated in the coherent memory region in the Trusted Firmware
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because it can be accessed by multple CPUs, either with caches enabled or
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disabled.
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typedef struct non_cpu_pwr_domain_node {
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typedef struct non_cpu_pwr_domain_node {
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/*
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* Index of the first CPU power domain node level 0 which has this node
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* as its parent.
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@ -1527,7 +1527,7 @@ typedef struct non_cpu_pwr_domain_node {
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/* For indexing the psci_lock array*/
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unsigned char lock_index;
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} non_cpu_pd_node_t;
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} non_cpu_pd_node_t;
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In order to move this data structure to normal memory, the use of each of its
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fields must be analyzed. Fields like `cpu_start_idx`, `ncpus`, `parent_node`
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@ -1659,7 +1659,7 @@ There is however a performance impact for bakery locks, due to:
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* Multiple cache line reads for each lock operation, since the bakery locks
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for each CPU are distributed across different cache lines.
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The implementation has been optimized to mimimize this additional overhead.
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The implementation has been optimized to minimize this additional overhead.
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Measurements indicate that when bakery locks are allocated in Normal memory, the
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minimum latency of acquiring a lock is on an average 3-4 micro seconds whereas
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in Device memory the same is 2 micro seconds. The measurements were done on the
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@ -359,7 +359,7 @@ for the security state specified in the `flags` parameter.
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Once the handler routine completes, execution will return to either the secure
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or non-secure state. The handler routine should return a pointer to
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`cpu_context` structure of the current CPU for the the target security state. It
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`cpu_context` structure of the current CPU for the target security state. It
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should treat all error conditions as critical errors and take appropriate action
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within its implementation e.g. use assertion failures.
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@ -430,8 +430,8 @@ must also be defined:
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If the platform needs to allocate data within the per-cpu data framework in
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BL31, it should define the following macro. Currently this is only required if
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the platform decides not to use the coherent memory section by undefining the
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USE_COHERENT_MEM build flag. In this case, the framework allocates the required
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memory within the the per-cpu data to minimize wastage.
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`USE_COHERENT_MEM` build flag. In this case, the framework allocates the
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required memory within the the per-cpu data to minimize wastage.
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* **#define : PLAT_PCPU_DATA_SIZE**
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@ -477,7 +477,7 @@ found in `plat/arm/board/<plat_name>/include/plat_macros.S`.
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BL1 by default implements the reset vector where execution starts from a cold
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or warm boot. BL31 can be optionally set as a reset vector using the
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RESET_TO_BL31 make variable.
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`RESET_TO_BL31` make variable.
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For each CPU, the reset vector code is responsible for the following tasks:
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@ -1437,7 +1437,7 @@ concept of a _power domain_. A _power domain_ is a CPU or a logical group of
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CPUs which share some state on which power management operations can be
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performed as specified by [PSCI]. Each CPU in the system is assigned a cpu
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index which is a unique number between `0` and `PLATFORM_CORE_COUNT - 1`.
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The _power domains_ are arranged in a hierarchial tree structure and
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The _power domains_ are arranged in a hierarchical tree structure and
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each _power domain_ can be identified in a system by the cpu index of any CPU
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that is part of that domain and a _power domain level_. A processing element
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(for example, a CPU) is at level 0. If the _power domain_ node above a CPU is
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@ -1725,7 +1725,7 @@ depends upon the id value as follows.
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Return : uint32_t
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This API returns the id of the highest priority pending interrupt at the
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platform IC. INTR_ID_UNAVAILABLE is returned when there is no interrupt
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platform IC. `INTR_ID_UNAVAILABLE` is returned when there is no interrupt
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pending.
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In the case of ARM standard platforms using GICv2, the _Highest Priority
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@ -127,7 +127,7 @@ initialization and call handler functions.
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typedef uint64_t (*rt_svc_handle)(uint32_t smc_fid,
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uint64_t x1, uint64_t x2,
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uint64_t x3, uint64_t x4,
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void *reserved,
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void *cookie,
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void *handle,
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uint64_t flags);
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@ -296,7 +296,7 @@ provide this information....
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- - - - - - - - - - - - - - - - - - - - - - - - - -
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_Copyright (c) 2014, ARM Limited and Contributors. All rights reserved._
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_Copyright (c) 2014-2015, ARM Limited and Contributors. All rights reserved._
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[Firmware Design]: ./firmware-design.md
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@ -304,7 +304,7 @@ _Copyright (c) 2014, ARM Limited and Contributors. All rights reserved._
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[`services`]: ../services
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[`services/std_svc/psci`]: ../services/std_svc/psci
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[`std_svc_setup.c`]: ../services/std_svc/std_svc_setup.c
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[`runtime_svc.h`]: ../include/runtime_svc.h
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[`runtime_svc.h`]: ../include/bl31/runtime_svc.h
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[`smcc_helpers.h`]: ../include/common/smcc_helpers.h
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[PSCI]: http://infocenter.arm.com/help/topic/com.arm.doc.den0022c/DEN0022C_Power_State_Coordination_Interface.pdf "Power State Coordination Interface PDD (ARM DEN 0022C)"
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[SMCCC]: http://infocenter.arm.com/help/topic/com.arm.doc.den0028a/index.html "SMC Calling Convention PDD (ARM DEN 0028A)"
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@ -132,7 +132,7 @@ Trusted Firmware source tree and follow these steps:
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* `build/<platform>/<build-type>/bl31.bin`
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where `<platform>` is the name of the chosen platform and `<build-type>` is
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either `debug` or `release`. A Firmare Image Package (FIP) will be created
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either `debug` or `release`. A Firmware Image Package (FIP) will be created
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as part of the build. It contains all boot loader images except for
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`bl1.bin`.
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@ -167,8 +167,8 @@ Trusted Firmware source tree and follow these steps:
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the specified binary in the final FIP image. Please note that BL32 will be
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included in the build, only if the `SPD` build option is specified.
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For example, specifying BL2=<path-to>/<bl2_image> in the build option, will
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skip compilation of BL2 source in trusted firmware, but include the BL2
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For example, specifying `BL2=<path-to>/<bl2_image>` in the build option,
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will skip compilation of BL2 source in trusted firmware, but include the BL2
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binary specified in the final FIP image.
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### Summary of build options
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@ -399,8 +399,8 @@ performed.
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* `SPIN_ON_BL1_EXIT`: This option introduces an infinite loop in BL1. It can
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take either 0 (no loop) or 1 (add a loop). 0 is the default. This loop stops
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execution in BL1 just before handing over to BL31. At this point, all
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firmware images have been loaded in memory and the MMU as well as the caches
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are turned off. Refer to the "Debugging options" section for more details.
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firmware images have been loaded in memory, and the MMU and caches are
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turned off. Refer to the "Debugging options" section for more details.
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* `EL3_PAYLOAD_BASE`: This option enables booting an EL3 payload instead of
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the normal boot flow. It must specify the entry point address of the EL3
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@ -516,7 +516,7 @@ View the contents of an existing Firmware package:
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- EL3 Runtime Firmware BL31: offset=0x8270, size=0xC218
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---------------------------
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Existing package entries can be individially updated:
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Existing package entries can be individually updated:
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# Change the BL2 from Debug to Release version
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./tools/fip_create/fip_create fip.bin --dump \
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@ -599,7 +599,7 @@ An additional boot loader binary file is created in the `build` directory:
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The FIP will now contain the additional BL32 image. Here is an example
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output from an FVP build in release mode including BL32 and using
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FVP_AARCH64_EFI.fd as BL33 image:
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`FVP_AARCH64_EFI.fd` as BL33 image:
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Firmware Image Package ToC:
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---------------------------
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@ -38,7 +38,7 @@
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#endif
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/*******************************************************************************
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* Number of power domains whose state this psci imp. can track
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* Number of power domains whose state this PSCI implementation can track
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******************************************************************************/
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#ifdef PLAT_NUM_PWR_DOMAINS
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#define PSCI_NUM_PWR_DOMAINS PLAT_NUM_PWR_DOMAINS
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@ -60,7 +60,7 @@
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#define PSCI_MAX_PWR_LVL 3
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/*******************************************************************************
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* Defines for runtime services func ids
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* Defines for runtime services function ids
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******************************************************************************/
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#define PSCI_VERSION 0x84000000
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#define PSCI_CPU_SUSPEND_AARCH32 0x84000001
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@ -255,7 +255,7 @@ typedef struct psci_cpu_data {
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/*******************************************************************************
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* Structure populated by platform specific code to export routines which
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* perform common low level pm functions
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* perform common low level power management functions
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******************************************************************************/
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typedef struct plat_psci_ops {
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void (*cpu_standby)(plat_local_state_t cpu_state);
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@ -276,7 +276,7 @@ typedef struct plat_psci_ops {
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/*******************************************************************************
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* Optional structure populated by the Secure Payload Dispatcher to be given a
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* chance to perform any bookkeeping before PSCI executes a power mgmt.
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* chance to perform any bookkeeping before PSCI executes a power management
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* operation. It also allows PSCI to determine certain properties of the SP e.g.
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* migrate capability etc.
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******************************************************************************/
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@ -139,7 +139,7 @@ endfunc plat_secondary_cold_boot_setup
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* For a warm boot, read the mailbox and return the address it contains.
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*
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* TODO: PSYSR is a common register and should be
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* accessed using locks. Since its not possible
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* accessed using locks. Since it is not possible
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* to use locks immediately after a cold reset
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* we are relying on the fact that after a cold
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* reset all cpus will read the same WK field
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@ -231,7 +231,7 @@ int32_t tspd_setup(void)
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return 1;
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/*
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* We could inspect the SP image and determine it's execution
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* We could inspect the SP image and determine its execution
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* state i.e whether AArch32 or AArch64. Assuming it's AArch64
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* for the time being.
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*/
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@ -461,7 +461,7 @@ uint64_t tspd_smc_handler(uint32_t smc_fid,
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#endif
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/*
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* These function IDs is used only by the SP to indicate it has
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* These function IDs are used only by the SP to indicate it has
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* finished:
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* 1. turning itself on in response to an earlier psci
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* cpu_on request
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@ -472,7 +472,7 @@ uint64_t tspd_smc_handler(uint32_t smc_fid,
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case TSP_RESUME_DONE:
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/*
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* These function IDs is used only by the SP to indicate it has
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* These function IDs are used only by the SP to indicate it has
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* finished:
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* 1. suspending itself after an earlier psci cpu_suspend
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* request.
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@ -206,10 +206,10 @@ int psci_cpu_on_start(unsigned long target_cpu,
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void psci_cpu_on_finish(unsigned int cpu_idx,
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psci_power_state_t *state_info);
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/* Private exported functions from psci_cpu_off.c */
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/* Private exported functions from psci_off.c */
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int psci_do_cpu_off(unsigned int end_pwrlvl);
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/* Private exported functions from psci_pwrlvl_suspend.c */
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/* Private exported functions from psci_suspend.c */
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void psci_cpu_suspend_start(entry_point_info_t *ep,
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unsigned int end_pwrlvl,
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psci_power_state_t *state_info,
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