feat(drivers/st/uart): add uart driver for STM32MP1
Add a UART/USART driver for STM32 with complete a hardware support; it used for STM32CubeProgrammer support with even parity. This driver is not used for console, which is already handle by a simple driver (drivers/st/uart/aarch32/stm32_console.S). Change-Id: Ia9266e5d177fe7fd09c8a15b81da1a05b1bc8b2d Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
This commit is contained in:
Nicolas Le Bayon
Patrick Delaunay
parent
1777ac11a5
commit
165ad5561e
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@ -14,6 +14,7 @@
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#include <drivers/st/stm32_gpio.h>
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#include <drivers/st/stm32mp_clkfunc.h>
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#define DT_UART_COMPAT "st,stm32h7-uart"
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/*
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* Get the frequency of an oscillator from its name in device tree.
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* @param name: oscillator name
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@ -297,3 +298,32 @@ int fdt_get_clock_id(int node)
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cuint++;
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return (int)fdt32_to_cpu(*cuint);
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}
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/*
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* Get the frequency of the specified UART instance.
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* @param instance: UART interface registers base address.
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* @return: clock frequency on success, 0 value on failure.
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*/
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unsigned long fdt_get_uart_clock_freq(uintptr_t instance)
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{
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void *fdt;
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int node;
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int clk_id;
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if (fdt_get_address(&fdt) == 0) {
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return 0UL;
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}
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/* Check for UART nodes */
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node = dt_match_instance_by_compatible(DT_UART_COMPAT, instance);
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if (node < 0) {
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return 0UL;
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}
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clk_id = fdt_get_clock_id(node);
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if (clk_id < 0) {
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return 0UL;
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}
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return stm32mp_clk_get_rate((unsigned long)clk_id);
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}
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@ -0,0 +1,404 @@
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/*
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* Copyright (c) 2021, STMicroelectronics - All Rights Reserved
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <assert.h>
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#include <errno.h>
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#include <string.h>
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#include <common/bl_common.h>
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#include <drivers/delay_timer.h>
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#include <drivers/st/stm32_uart.h>
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#include <drivers/st/stm32_uart_regs.h>
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#include <drivers/st/stm32mp_clkfunc.h>
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#include <lib/mmio.h>
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#include <platform_def.h>
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/* UART time-out value */
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#define STM32_UART_TIMEOUT_US 20000U
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/* Mask to clear ALL the configuration registers */
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#define STM32_UART_CR1_FIELDS \
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(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | \
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USART_CR1_RE | USART_CR1_OVER8 | USART_CR1_FIFOEN)
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#define STM32_UART_CR2_FIELDS \
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(USART_CR2_SLVEN | USART_CR2_DIS_NSS | USART_CR2_ADDM7 | \
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USART_CR2_LBDL | USART_CR2_LBDIE | USART_CR2_LBCL | \
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USART_CR2_CPHA | USART_CR2_CPOL | USART_CR2_CLKEN | \
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USART_CR2_STOP | USART_CR2_LINEN | USART_CR2_SWAP | \
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USART_CR2_RXINV | USART_CR2_TXINV | USART_CR2_DATAINV | \
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USART_CR2_MSBFIRST | USART_CR2_ABREN | USART_CR2_ABRMODE | \
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USART_CR2_RTOEN | USART_CR2_ADD)
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#define STM32_UART_CR3_FIELDS \
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(USART_CR3_EIE | USART_CR3_IREN | USART_CR3_IRLP | \
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USART_CR3_HDSEL | USART_CR3_NACK | USART_CR3_SCEN | \
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USART_CR3_DMAR | USART_CR3_DMAT | USART_CR3_RTSE | \
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USART_CR3_CTSE | USART_CR3_CTSIE | USART_CR3_ONEBIT | \
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USART_CR3_OVRDIS | USART_CR3_DDRE | USART_CR3_DEM | \
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USART_CR3_DEP | USART_CR3_SCARCNT | USART_CR3_WUS | \
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USART_CR3_WUFIE | USART_CR3_TXFTIE | USART_CR3_TCBGTIE | \
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USART_CR3_RXFTCFG | USART_CR3_RXFTIE | USART_CR3_TXFTCFG)
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#define STM32_UART_ISR_ERRORS \
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(USART_ISR_ORE | USART_ISR_NE | USART_ISR_FE | USART_ISR_PE)
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static const uint16_t presc_table[STM32_UART_PRESCALER_NB] = {
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1U, 2U, 4U, 6U, 8U, 10U, 12U, 16U, 32U, 64U, 128U, 256U
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};
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/* @brief BRR division operation to set BRR register in 8-bit oversampling
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* mode.
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* @param clockfreq: UART clock.
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* @param baud_rate: Baud rate set by the user.
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* @param prescaler: UART prescaler value.
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* @retval Division result.
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*/
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static uint32_t uart_div_sampling8(unsigned long clockfreq,
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uint32_t baud_rate,
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uint32_t prescaler)
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{
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uint32_t scaled_freq = clockfreq / presc_table[prescaler];
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return ((scaled_freq * 2) + (baud_rate / 2)) / baud_rate;
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}
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/* @brief BRR division operation to set BRR register in 16-bit oversampling
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* mode.
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* @param clockfreq: UART clock.
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* @param baud_rate: Baud rate set by the user.
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* @param prescaler: UART prescaler value.
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* @retval Division result.
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*/
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static uint32_t uart_div_sampling16(unsigned long clockfreq,
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uint32_t baud_rate,
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uint32_t prescaler)
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{
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uint32_t scaled_freq = clockfreq / presc_table[prescaler];
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return (scaled_freq + (baud_rate / 2)) / baud_rate;
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}
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/*
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* @brief Return the UART clock frequency.
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* @param huart: UART handle.
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* @retval Frequency value in Hz.
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*/
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static unsigned long uart_get_clock_freq(struct stm32_uart_handle_s *huart)
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{
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return fdt_get_uart_clock_freq((uintptr_t)huart->base);
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}
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/*
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* @brief Configure the UART peripheral.
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* @param huart: UART handle.
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* @retval UART status.
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*/
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static int uart_set_config(struct stm32_uart_handle_s *huart,
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const struct stm32_uart_init_s *init)
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{
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uint32_t tmpreg;
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unsigned long clockfreq;
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uint32_t brrtemp;
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/*
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* ---------------------- USART CR1 Configuration --------------------
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* Clear M, PCE, PS, TE, RE and OVER8 bits and configure
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* the UART word length, parity, mode and oversampling:
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* - set the M bits according to init->word_length value,
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* - set PCE and PS bits according to init->parity value,
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* - set TE and RE bits according to init->mode value,
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* - set OVER8 bit according to init->over_sampling value.
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*/
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tmpreg = init->word_length |
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init->parity |
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init->mode |
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init->over_sampling |
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init->fifo_mode;
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mmio_clrsetbits_32(huart->base + USART_CR1, STM32_UART_CR1_FIELDS, tmpreg);
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/*
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* --------------------- USART CR2 Configuration ---------------------
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* Configure the UART Stop Bits: Set STOP[13:12] bits according
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* to init->stop_bits value.
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*/
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mmio_clrsetbits_32(huart->base + USART_CR2, STM32_UART_CR2_FIELDS,
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init->stop_bits);
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/*
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* --------------------- USART CR3 Configuration ---------------------
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* Configure:
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* - UART HardWare Flow Control: set CTSE and RTSE bits according
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* to init->hw_flow_control value,
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* - one-bit sampling method versus three samples' majority rule
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* according to init->one_bit_sampling (not applicable to
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* LPUART),
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* - set TXFTCFG bit according to init->tx_fifo_threshold value,
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* - set RXFTCFG bit according to init->rx_fifo_threshold value.
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*/
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tmpreg = init->hw_flow_control | init->one_bit_sampling;
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if (init->fifo_mode == USART_CR1_FIFOEN) {
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tmpreg |= init->tx_fifo_threshold |
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init->rx_fifo_threshold;
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}
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mmio_clrsetbits_32(huart->base + USART_CR3, STM32_UART_CR3_FIELDS, tmpreg);
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/*
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* --------------------- USART PRESC Configuration -------------------
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* Configure UART Clock Prescaler : set PRESCALER according to
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* init->prescaler value.
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*/
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assert(init->prescaler < STM32_UART_PRESCALER_NB);
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mmio_clrsetbits_32(huart->base + USART_PRESC, USART_PRESC_PRESCALER,
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init->prescaler);
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/*---------------------- USART BRR configuration --------------------*/
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clockfreq = uart_get_clock_freq(huart);
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if (clockfreq == 0UL) {
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return -ENODEV;
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}
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if (init->over_sampling == STM32_UART_OVERSAMPLING_8) {
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uint32_t usartdiv = uart_div_sampling8(clockfreq,
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init->baud_rate,
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init->prescaler);
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brrtemp = (usartdiv & USART_BRR_DIV_MANTISSA) |
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((usartdiv & USART_BRR_DIV_FRACTION) >> 1);
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} else {
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brrtemp = uart_div_sampling16(clockfreq,
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init->baud_rate,
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init->prescaler) &
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(USART_BRR_DIV_FRACTION | USART_BRR_DIV_MANTISSA);
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}
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mmio_write_32(huart->base + USART_BRR, brrtemp);
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return 0;
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}
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/*
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* @brief Handle UART communication timeout.
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* @param huart: UART handle.
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* @param flag: Specifies the UART flag to check.
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* @retval UART status.
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*/
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static int stm32_uart_wait_flag(struct stm32_uart_handle_s *huart, uint32_t flag)
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{
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uint64_t timeout_ref = timeout_init_us(STM32_UART_TIMEOUT_US);
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while ((mmio_read_32(huart->base + USART_ISR) & flag) == 0U) {
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if (timeout_elapsed(timeout_ref)) {
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return -ETIMEDOUT;
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}
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}
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return 0;
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}
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/*
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* @brief Check the UART idle State.
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* @param huart: UART handle.
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* @retval UART status.
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*/
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static int stm32_uart_check_idle(struct stm32_uart_handle_s *huart)
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{
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int ret;
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/* Check if the transmitter is enabled */
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if ((mmio_read_32(huart->base + USART_CR1) & USART_CR1_TE) == USART_CR1_TE) {
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ret = stm32_uart_wait_flag(huart, USART_ISR_TEACK);
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if (ret != 0) {
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return ret;
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}
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}
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/* Check if the receiver is enabled */
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if ((mmio_read_32(huart->base + USART_CR1) & USART_CR1_RE) == USART_CR1_RE) {
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ret = stm32_uart_wait_flag(huart, USART_ISR_REACK);
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if (ret != 0) {
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return ret;
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}
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}
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return 0;
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}
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/*
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* @brief Compute RDR register mask depending on word length.
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* @param huart: UART handle.
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* @retval Mask value.
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*/
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static unsigned int stm32_uart_rdr_mask(const struct stm32_uart_init_s *init)
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{
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unsigned int mask = 0U;
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switch (init->word_length) {
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case STM32_UART_WORDLENGTH_9B:
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mask = GENMASK(8, 0);
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break;
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case STM32_UART_WORDLENGTH_8B:
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mask = GENMASK(7, 0);
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break;
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case STM32_UART_WORDLENGTH_7B:
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mask = GENMASK(6, 0);
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break;
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default:
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break; /* not reached */
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}
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if (init->parity != STM32_UART_PARITY_NONE) {
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mask >>= 1;
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}
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return mask;
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}
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/*
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* @brief Check interrupt and status errors.
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* @retval True if error detected, false otherwise.
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*/
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static bool stm32_uart_error_detected(struct stm32_uart_handle_s *huart)
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{
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return (mmio_read_32(huart->base + USART_ISR) & STM32_UART_ISR_ERRORS) != 0U;
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}
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/*
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* @brief Clear status errors.
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*/
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static void stm32_uart_error_clear(struct stm32_uart_handle_s *huart)
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{
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mmio_write_32(huart->base + USART_ICR, STM32_UART_ISR_ERRORS);
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}
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/*
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* @brief Stop the UART.
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* @param base: UART base address.
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*/
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void stm32_uart_stop(uintptr_t base)
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{
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mmio_clrbits_32(base + USART_CR1, USART_CR1_UE);
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}
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/*
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* @brief Initialize UART.
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* @param huart: UART handle.
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* @param base_addr: base address of UART.
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* @param init: UART initialization parameter.
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* @retval UART status.
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*/
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int stm32_uart_init(struct stm32_uart_handle_s *huart,
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uintptr_t base_addr,
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const struct stm32_uart_init_s *init)
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{
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int ret;
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if (huart == NULL || init == NULL || base_addr == 0U) {
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return -EINVAL;
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}
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huart->base = base_addr;
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/* Disable the peripheral */
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stm32_uart_stop(huart->base);
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/* Computation of UART mask to apply to RDR register */
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huart->rdr_mask = stm32_uart_rdr_mask(init);
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/* Init the peripheral */
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ret = uart_set_config(huart, init);
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if (ret != 0) {
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return ret;
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}
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/* Enable the peripheral */
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mmio_setbits_32(huart->base + USART_CR1, USART_CR1_UE);
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/* TEACK and/or REACK to check */
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return stm32_uart_check_idle(huart);
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}
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/*
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* @brief Transmit one data in no blocking mode.
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* @param huart: UART handle.
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* @param c: data to sent.
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* @retval UART status.
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*/
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int stm32_uart_putc(struct stm32_uart_handle_s *huart, int c)
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{
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int ret;
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if (huart == NULL) {
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return -EINVAL;
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}
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ret = stm32_uart_wait_flag(huart, USART_ISR_TXE);
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if (ret != 0) {
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return ret;
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}
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mmio_write_32(huart->base + USART_TDR, c);
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if (stm32_uart_error_detected(huart)) {
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stm32_uart_error_clear(huart);
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return -EFAULT;
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}
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return 0;
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}
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/*
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* @brief Flush TX Transmit fifo
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* @param huart: UART handle.
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* @retval UART status.
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*/
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int stm32_uart_flush(struct stm32_uart_handle_s *huart)
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{
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int ret;
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if (huart == NULL) {
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return -EINVAL;
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}
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ret = stm32_uart_wait_flag(huart, USART_ISR_TXE);
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if (ret != 0) {
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return ret;
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}
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return stm32_uart_wait_flag(huart, USART_ISR_TC);
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}
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/*
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* @brief Receive a data in no blocking mode.
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* @retval value if >0 or UART status.
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*/
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int stm32_uart_getc(struct stm32_uart_handle_s *huart)
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{
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uint32_t data;
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if (huart == NULL) {
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return -EINVAL;
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}
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/* Check if data is available */
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if ((mmio_read_32(huart->base + USART_ISR) & USART_ISR_RXNE) == 0U) {
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return -EAGAIN;
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}
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data = mmio_read_32(huart->base + USART_RDR) & huart->rdr_mask;
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if (stm32_uart_error_detected(huart)) {
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stm32_uart_error_clear(huart);
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return -EFAULT;
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}
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return (int)data;
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}
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@ -0,0 +1,170 @@
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/*
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* Copyright (c) 2021, STMicroelectronics - All Rights Reserved
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef STM32_UART_H
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#define STM32_UART_H
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|
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/* UART word length */
|
||||
#define STM32_UART_WORDLENGTH_7B USART_CR1_M1
|
||||
#define STM32_UART_WORDLENGTH_8B 0x00000000U
|
||||
#define STM32_UART_WORDLENGTH_9B USART_CR1_M0
|
||||
|
||||
/* UART number of stop bits */
|
||||
#define STM32_UART_STOPBITS_0_5 USART_CR2_STOP_0
|
||||
#define STM32_UART_STOPBITS_1 0x00000000U
|
||||
#define STM32_UART_STOPBITS_1_5 (USART_CR2_STOP_0 | USART_CR2_STOP_1)
|
||||
#define STM32_UART_STOPBITS_2 USART_CR2_STOP_1
|
||||
|
||||
/* UART parity */
|
||||
#define STM32_UART_PARITY_NONE 0x00000000U
|
||||
#define STM32_UART_PARITY_EVEN USART_CR1_PCE
|
||||
#define STM32_UART_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS)
|
||||
|
||||
/* UART transfer mode */
|
||||
#define STM32_UART_MODE_RX USART_CR1_RE
|
||||
#define STM32_UART_MODE_TX USART_CR1_TE
|
||||
#define STM32_UART_MODE_TX_RX (USART_CR1_TE | USART_CR1_RE)
|
||||
|
||||
/* UART hardware flow control */
|
||||
#define STM32_UART_HWCONTROL_NONE 0x00000000U
|
||||
#define STM32_UART_HWCONTROL_RTS USART_CR3_RTSE
|
||||
#define STM32_UART_HWCONTROL_CTS USART_CR3_CTSE
|
||||
#define STM32_UART_HWCONTROL_RTS_CTS (USART_CR3_RTSE | USART_CR3_CTSE)
|
||||
|
||||
/* UART over sampling */
|
||||
#define STM32_UART_OVERSAMPLING_16 0x00000000U
|
||||
#define STM32_UART_OVERSAMPLING_8 USART_CR1_OVER8
|
||||
|
||||
/* UART prescaler */
|
||||
#define STM32_UART_PRESCALER_DIV1 0x00000000U
|
||||
#define STM32_UART_PRESCALER_DIV2 0x00000001U
|
||||
#define STM32_UART_PRESCALER_DIV4 0x00000002U
|
||||
#define STM32_UART_PRESCALER_DIV6 0x00000003U
|
||||
#define STM32_UART_PRESCALER_DIV8 0x00000004U
|
||||
#define STM32_UART_PRESCALER_DIV10 0x00000005U
|
||||
#define STM32_UART_PRESCALER_DIV12 0x00000006U
|
||||
#define STM32_UART_PRESCALER_DIV16 0x00000007U
|
||||
#define STM32_UART_PRESCALER_DIV32 0x00000008U
|
||||
#define STM32_UART_PRESCALER_DIV64 0x00000009U
|
||||
#define STM32_UART_PRESCALER_DIV128 0x0000000AU
|
||||
#define STM32_UART_PRESCALER_DIV256 0x0000000BU
|
||||
#define STM32_UART_PRESCALER_NB 0x0000000CU
|
||||
|
||||
/* UART fifo mode */
|
||||
#define STM32_UART_FIFOMODE_EN USART_CR1_FIFOEN
|
||||
#define STM32_UART_FIFOMODE_DIS 0x00000000U
|
||||
|
||||
/* UART TXFIFO threshold level */
|
||||
#define STM32_UART_TXFIFO_THRESHOLD_1EIGHTHFULL 0x00000000U
|
||||
#define STM32_UART_TXFIFO_THRESHOLD_1QUARTERFUL USART_CR3_TXFTCFG_0
|
||||
#define STM32_UART_TXFIFO_THRESHOLD_HALFFULL USART_CR3_TXFTCFG_1
|
||||
#define STM32_UART_TXFIFO_THRESHOLD_3QUARTERSFULL (USART_CR3_TXFTCFG_0 | USART_CR3_TXFTCFG_1)
|
||||
#define STM32_UART_TXFIFO_THRESHOLD_7EIGHTHFULL USART_CR3_TXFTCFG_2
|
||||
#define STM32_UART_TXFIFO_THRESHOLD_EMPTY (USART_CR3_TXFTCFG_2 | USART_CR3_TXFTCFG_0)
|
||||
|
||||
/* UART RXFIFO threshold level */
|
||||
#define STM32_UART_RXFIFO_THRESHOLD_1EIGHTHFULL 0x00000000U
|
||||
#define STM32_UART_RXFIFO_THRESHOLD_1QUARTERFULL USART_CR3_RXFTCFG_0
|
||||
#define STM32_UART_RXFIFO_THRESHOLD_HALFFULL USART_CR3_RXFTCFG_1
|
||||
#define STM32_UART_RXFIFO_THRESHOLD_3QUARTERSFULL (USART_CR3_RXFTCFG_0 | USART_CR3_RXFTCFG_1)
|
||||
#define STM32_UART_RXFIFO_THRESHOLD_7EIGHTHFULL USART_CR3_RXFTCFG_2
|
||||
#define STM32_UART_RXFIFO_THRESHOLD_FULL (USART_CR3_RXFTCFG_2 | USART_CR3_RXFTCFG_0)
|
||||
|
||||
struct stm32_uart_init_s {
|
||||
uint32_t baud_rate; /*
|
||||
* Configures the UART communication
|
||||
* baud rate.
|
||||
*/
|
||||
|
||||
uint32_t word_length; /*
|
||||
* Specifies the number of data bits
|
||||
* transmitted or received in a frame.
|
||||
* This parameter can be a value of
|
||||
* @ref STM32_UART_WORDLENGTH_*.
|
||||
*/
|
||||
|
||||
uint32_t stop_bits; /*
|
||||
* Specifies the number of stop bits
|
||||
* transmitted. This parameter can be
|
||||
* a value of @ref STM32_UART_STOPBITS_*.
|
||||
*/
|
||||
|
||||
uint32_t parity; /*
|
||||
* Specifies the parity mode.
|
||||
* This parameter can be a value of
|
||||
* @ref STM32_UART_PARITY_*.
|
||||
*/
|
||||
|
||||
uint32_t mode; /*
|
||||
* Specifies whether the receive or
|
||||
* transmit mode is enabled or
|
||||
* disabled. This parameter can be a
|
||||
* value of @ref @ref STM32_UART_MODE_*.
|
||||
*/
|
||||
|
||||
uint32_t hw_flow_control; /*
|
||||
* Specifies whether the hardware flow
|
||||
* control mode is enabled or
|
||||
* disabled. This parameter can be a
|
||||
* value of @ref STM32_UARTHWCONTROL_*.
|
||||
*/
|
||||
|
||||
uint32_t over_sampling; /*
|
||||
* Specifies whether the over sampling
|
||||
* 8 is enabled or disabled.
|
||||
* This parameter can be a value of
|
||||
* @ref STM32_UART_OVERSAMPLING_*.
|
||||
*/
|
||||
|
||||
uint32_t one_bit_sampling; /*
|
||||
* Specifies whether a single sample
|
||||
* or three samples' majority vote is
|
||||
* selected. This parameter can be 0
|
||||
* or USART_CR3_ONEBIT.
|
||||
*/
|
||||
|
||||
uint32_t prescaler; /*
|
||||
* Specifies the prescaler value used
|
||||
* to divide the UART clock source.
|
||||
* This parameter can be a value of
|
||||
* @ref STM32_UART_PRESCALER_*.
|
||||
*/
|
||||
|
||||
uint32_t fifo_mode; /*
|
||||
* Specifies if the FIFO mode will be
|
||||
* used. This parameter can be a value
|
||||
* of @ref STM32_UART_FIFOMODE_*.
|
||||
*/
|
||||
|
||||
uint32_t tx_fifo_threshold; /*
|
||||
* Specifies the TXFIFO threshold
|
||||
* level. This parameter can be a
|
||||
* value of @ref
|
||||
* STM32_UART_TXFIFO_THRESHOLD_*.
|
||||
*/
|
||||
|
||||
uint32_t rx_fifo_threshold; /*
|
||||
* Specifies the RXFIFO threshold
|
||||
* level. This parameter can be a
|
||||
* value of @ref
|
||||
* STM32_UART_RXFIFO_THRESHOLD_*.
|
||||
*/
|
||||
};
|
||||
|
||||
struct stm32_uart_handle_s {
|
||||
uint32_t base;
|
||||
uint32_t rdr_mask;
|
||||
};
|
||||
|
||||
int stm32_uart_init(struct stm32_uart_handle_s *huart,
|
||||
uintptr_t base_addr,
|
||||
const struct stm32_uart_init_s *init);
|
||||
void stm32_uart_stop(uintptr_t base_addr);
|
||||
int stm32_uart_putc(struct stm32_uart_handle_s *huart, int c);
|
||||
int stm32_uart_flush(struct stm32_uart_handle_s *huart);
|
||||
int stm32_uart_getc(struct stm32_uart_handle_s *huart);
|
||||
|
||||
#endif /* STM32_UART_H */
|
||||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* Copyright (c) 2017-2020, STMicroelectronics - All Rights Reserved
|
||||
* Copyright (c) 2017-2021, STMicroelectronics - All Rights Reserved
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
|
@ -26,5 +26,6 @@ const fdt32_t *fdt_rcc_read_prop(const char *prop_name, int *lenp);
|
|||
bool fdt_get_rcc_secure_status(void);
|
||||
|
||||
int fdt_get_clock_id(int node);
|
||||
unsigned long fdt_get_uart_clock_freq(uintptr_t instance);
|
||||
|
||||
#endif /* STM32MP_CLKFUNC_H */
|
||||
|
|
|
|||
Loading…
Reference in New Issue