ti: k3: common: Set L2 latency on A72 cores
The Cortex-A72 based cores on K3 platforms can be clocked fast enough that an extra latency cycle is needed to ensure correct L2 access. Set the latency here for all A72 cores. Signed-off-by: Andrew F. Davis <afd@ti.com> Change-Id: Id534316dec1c1f326908efbfd964f219cda7386a
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@ -6,6 +6,8 @@
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#include <arch.h>
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#include <arch.h>
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#include <asm_macros.S>
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#include <asm_macros.S>
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#include <cortex_a72.h>
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#include <cpu_macros.S>
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#include <platform_def.h>
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#include <platform_def.h>
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#define K3_BOOT_REASON_COLD_RESET 0x1
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#define K3_BOOT_REASON_COLD_RESET 0x1
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@ -89,6 +91,26 @@ out:
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ret
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ret
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endfunc plat_my_core_pos
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endfunc plat_my_core_pos
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/* --------------------------------------------------------------------
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* This handler does the following:
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* - Set the L2 Data RAM latency to 2 (i.e. 3 cycles) for Cortex-A72
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* --------------------------------------------------------------------
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*/
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.globl plat_reset_handler
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func plat_reset_handler
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/* Only on Cortex-A72 */
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jump_if_cpu_midr CORTEX_A72_MIDR, a72
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ret
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/* Cortex-A72 specific settings */
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a72:
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mrs x0, CORTEX_A72_L2CTLR_EL1
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orr x0, x0, #(CORTEX_A72_L2_DATA_RAM_LATENCY_3_CYCLES << CORTEX_A72_L2CTLR_DATA_RAM_LATENCY_SHIFT)
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msr CORTEX_A72_L2CTLR_EL1, x0
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isb
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ret
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endfunc plat_reset_handler
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/* ---------------------------------------------
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/* ---------------------------------------------
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* int plat_crash_console_init(void)
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* int plat_crash_console_init(void)
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* Function to initialize the crash console
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* Function to initialize the crash console
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