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FIXUP: rockchip: rk3399: fix the incorrect bit during m0_init 

We found that the DUT will be hanged if we don't set the bit_1 of the
PMUCRU_GATEDIS_CON0. But, from the TRM, there is weird that the bit_1
is set the clk_center1_gating_dis, not clk_pmum0_gating_dis. Is the
TRM incorrect? We need to check it with the IC team and re-clean the
commit message and explain it tomorrow.

Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
This commit is contained in:
Xing Zheng 2016-12-20 20:44:41 +08:00
parent ca9286c68a
commit 175476f9e5
1 changed files with 2 additions and 1 deletions
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3
plat/rockchip/rk3399/drivers/pmu/m0_ctl.c
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@ -53,7 +53,8 @@ void m0_init(void)
0xf, 0));
/* gating disable for M0 */
mmio_write_32(PMUCRU_BASE + PMUCRU_GATEDIS_CON0, BIT_WITH_WMSK(0));
mmio_write_32(PMUCRU_BASE + PMUCRU_GATEDIS_CON0,
BITS_WITH_WMASK(0x3, 0x3, 0));
/*
* To switch the parent to xin24M and div == 1,