plat/qemu: move gicv2 codes to separate file
This file moves gicv2 codes to a new separate files, target is to add gicv3 support later. Signed-off-by: Hongbo Zhang <hongbo.zhang@linaro.org> Reviewed-by: Radoslaw Biernacki <radoslaw.biernacki@linaro.org> Tested-by: Radoslaw Biernacki <radoslaw.biernacki@linaro.org> Change-Id: I30eb1fda5ea5c2b35d79360c52f46601cbca1bcc
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@ -1,5 +1,5 @@
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/*
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/*
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* Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
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*
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*
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* SPDX-License-Identifier: BSD-3-Clause
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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*/
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@ -219,6 +219,30 @@
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#define QEMU_IRQ_SEC_SGI_6 14
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#define QEMU_IRQ_SEC_SGI_6 14
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#define QEMU_IRQ_SEC_SGI_7 15
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#define QEMU_IRQ_SEC_SGI_7 15
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/******************************************************************************
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* On a GICv2 system, the Group 1 secure interrupts are treated as Group 0
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* interrupts.
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*****************************************************************************/
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#define PLATFORM_G1S_PROPS(grp) \
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INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_0, GIC_HIGHEST_SEC_PRIORITY, \
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grp, GIC_INTR_CFG_EDGE), \
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INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY, \
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grp, GIC_INTR_CFG_EDGE), \
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INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY, \
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grp, GIC_INTR_CFG_EDGE), \
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INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_3, GIC_HIGHEST_SEC_PRIORITY, \
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grp, GIC_INTR_CFG_EDGE), \
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INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_4, GIC_HIGHEST_SEC_PRIORITY, \
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grp, GIC_INTR_CFG_EDGE), \
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INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_5, GIC_HIGHEST_SEC_PRIORITY, \
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grp, GIC_INTR_CFG_EDGE), \
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INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, \
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grp, GIC_INTR_CFG_EDGE), \
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INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY, \
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grp, GIC_INTR_CFG_EDGE)
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#define PLATFORM_G0_PROPS(grp)
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/*
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/*
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* DT related constants
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* DT related constants
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*/
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*/
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@ -1,5 +1,5 @@
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#
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#
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# Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved.
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# Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved.
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#
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#
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# SPDX-License-Identifier: BSD-3-Clause
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# SPDX-License-Identifier: BSD-3-Clause
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#
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#
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@ -120,20 +120,22 @@ ifeq ($(add-lib-optee),yes)
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BL2_SOURCES += lib/optee/optee_utils.c
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BL2_SOURCES += lib/optee/optee_utils.c
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endif
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endif
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QEMU_GIC_SOURCES := drivers/arm/gic/v2/gicv2_helpers.c \
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drivers/arm/gic/v2/gicv2_main.c \
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drivers/arm/gic/common/gic_common.c \
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plat/common/plat_gicv2.c \
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plat/qemu/qemu_gicv2.c
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ifeq (${ARM_ARCH_MAJOR},8)
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ifeq (${ARM_ARCH_MAJOR},8)
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BL31_SOURCES += lib/cpus/aarch64/aem_generic.S \
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BL31_SOURCES += lib/cpus/aarch64/aem_generic.S \
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lib/cpus/aarch64/cortex_a53.S \
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lib/cpus/aarch64/cortex_a53.S \
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lib/cpus/aarch64/cortex_a57.S \
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lib/cpus/aarch64/cortex_a57.S \
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drivers/arm/gic/v2/gicv2_helpers.c \
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drivers/arm/gic/v2/gicv2_main.c \
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drivers/arm/gic/common/gic_common.c \
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plat/common/plat_gicv2.c \
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plat/common/plat_psci_common.c \
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plat/common/plat_psci_common.c \
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plat/qemu/qemu_pm.c \
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plat/qemu/qemu_pm.c \
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plat/qemu/topology.c \
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plat/qemu/topology.c \
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plat/qemu/aarch64/plat_helpers.S \
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plat/qemu/aarch64/plat_helpers.S \
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plat/qemu/qemu_bl31_setup.c
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plat/qemu/qemu_bl31_setup.c \
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${QEMU_GIC_SOURCES}
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endif
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endif
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# Add the build options to pack Trusted OS Extra1 and Trusted OS Extra2 images
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# Add the build options to pack Trusted OS Extra1 and Trusted OS Extra2 images
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@ -1,16 +1,12 @@
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/*
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/*
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* Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
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*
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*
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* SPDX-License-Identifier: BSD-3-Clause
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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*/
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#include <assert.h>
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#include <assert.h>
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#include <platform_def.h>
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#include <common/bl_common.h>
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#include <common/bl_common.h>
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#include <drivers/arm/gic_common.h>
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#include <drivers/arm/gicv2.h>
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#include <plat/common/platform.h>
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#include <plat/common/platform.h>
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#include "qemu_private.h"
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#include "qemu_private.h"
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@ -73,49 +69,9 @@ void bl31_plat_arch_setup(void)
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BL_COHERENT_RAM_BASE, BL_COHERENT_RAM_END);
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BL_COHERENT_RAM_BASE, BL_COHERENT_RAM_END);
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}
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}
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/******************************************************************************
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* On a GICv2 system, the Group 1 secure interrupts are treated as Group 0
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* interrupts.
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*****************************************************************************/
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#define PLATFORM_G1S_PROPS(grp) \
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INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_0, GIC_HIGHEST_SEC_PRIORITY, \
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grp, GIC_INTR_CFG_EDGE), \
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INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY, \
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grp, GIC_INTR_CFG_EDGE), \
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INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY, \
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grp, GIC_INTR_CFG_EDGE), \
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INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_3, GIC_HIGHEST_SEC_PRIORITY, \
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grp, GIC_INTR_CFG_EDGE), \
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INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_4, GIC_HIGHEST_SEC_PRIORITY, \
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grp, GIC_INTR_CFG_EDGE), \
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INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_5, GIC_HIGHEST_SEC_PRIORITY, \
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grp, GIC_INTR_CFG_EDGE), \
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INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, \
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grp, GIC_INTR_CFG_EDGE), \
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INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY, \
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grp, GIC_INTR_CFG_EDGE)
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#define PLATFORM_G0_PROPS(grp)
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static const interrupt_prop_t qemu_interrupt_props[] = {
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PLATFORM_G1S_PROPS(GICV2_INTR_GROUP0),
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PLATFORM_G0_PROPS(GICV2_INTR_GROUP0)
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};
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static const struct gicv2_driver_data plat_gicv2_driver_data = {
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.gicd_base = GICD_BASE,
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.gicc_base = GICC_BASE,
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.interrupt_props = qemu_interrupt_props,
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.interrupt_props_num = ARRAY_SIZE(qemu_interrupt_props),
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};
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void bl31_platform_setup(void)
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void bl31_platform_setup(void)
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{
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{
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/* Initialize the gic cpu and distributor interfaces */
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plat_qemu_gic_init();
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gicv2_driver_init(&plat_gicv2_driver_data);
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gicv2_distif_init();
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gicv2_pcpu_distif_init();
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gicv2_cpuif_enable();
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}
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}
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unsigned int plat_get_syscnt_freq2(void)
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unsigned int plat_get_syscnt_freq2(void)
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@ -0,0 +1,39 @@
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/*
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* Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <drivers/arm/gicv2.h>
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#include <drivers/arm/gic_common.h>
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#include <platform_def.h>
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static const interrupt_prop_t qemu_interrupt_props[] = {
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PLATFORM_G1S_PROPS(GICV2_INTR_GROUP0),
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PLATFORM_G0_PROPS(GICV2_INTR_GROUP0)
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};
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static const struct gicv2_driver_data plat_gicv2_driver_data = {
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.gicd_base = GICD_BASE,
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.gicc_base = GICC_BASE,
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.interrupt_props = qemu_interrupt_props,
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.interrupt_props_num = ARRAY_SIZE(qemu_interrupt_props),
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};
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void plat_qemu_gic_init(void)
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{
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/* Initialize the gic cpu and distributor interfaces */
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gicv2_driver_init(&plat_gicv2_driver_data);
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gicv2_distif_init();
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gicv2_pcpu_distif_init();
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gicv2_cpuif_enable();
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}
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void qemu_pwr_gic_on_finish(void)
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{
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/* TODO: This setup is needed only after a cold boot */
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gicv2_pcpu_distif_init();
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/* Enable the gic cpu interface */
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gicv2_cpuif_enable();
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}
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/*
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/*
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* Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
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*
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*
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* SPDX-License-Identifier: BSD-3-Clause
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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*/
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#include <assert.h>
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#include <assert.h>
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#include <platform_def.h>
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#include <platform_def.h>
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#include <arch_helpers.h>
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#include <arch_helpers.h>
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#include <common/debug.h>
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#include <common/debug.h>
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#include <drivers/arm/gicv2.h>
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#include <lib/psci/psci.h>
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#include <lib/psci/psci.h>
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#include <plat/common/platform.h>
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#include <plat/common/platform.h>
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#include "qemu_private.h"
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/*
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/*
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* The secure entry point to be used on warm reset.
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* The secure entry point to be used on warm reset.
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*/
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*/
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@ -173,11 +173,7 @@ void qemu_pwr_domain_on_finish(const psci_power_state_t *target_state)
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assert(target_state->pwr_domain_state[MPIDR_AFFLVL0] ==
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assert(target_state->pwr_domain_state[MPIDR_AFFLVL0] ==
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PLAT_LOCAL_STATE_OFF);
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PLAT_LOCAL_STATE_OFF);
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/* TODO: This setup is needed only after a cold boot */
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qemu_pwr_gic_on_finish();
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gicv2_pcpu_distif_init();
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/* Enable the gic cpu interface */
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gicv2_cpuif_enable();
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}
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}
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/*******************************************************************************
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/*******************************************************************************
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@ -1,5 +1,5 @@
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/*
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/*
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* Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
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*
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*
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* SPDX-License-Identifier: BSD-3-Clause
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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*/
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@ -33,4 +33,7 @@ int dt_add_psci_cpu_enable_methods(void *fdt);
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void qemu_console_init(void);
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void qemu_console_init(void);
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void plat_qemu_gic_init(void);
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void qemu_pwr_gic_on_finish(void);
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#endif /* QEMU_PRIVATE_H */
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#endif /* QEMU_PRIVATE_H */
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