plat: imx8m: Add the basic support for imx8mm
The i.MX8M Mini is new SOC of the i.MX8M family. it is focused on delivering the latest and greatest video and audio experience combining state-of-the-art media-specific features with high-performance processing while optimized for lowest power consumption. The i.MX 8M Mini Media Applications Processor is 14nm FinFET product of the growing i.MX8M family targeting the consumer & industrial market. It is built in 14LPP to achieve both high performance and low power consumption and relies on a powerful fully coherent core complex based on a quad Cortex-A53 cluster with video and graphics accelerators this patch add the basic support for i.MX8MM. Signed-off-by: Jacky Bai <ping.bai@nxp.com>
This commit is contained in:
Jacky Bai
parent
e8837b0aef
commit
179f82a2c6
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@ -31,6 +31,7 @@ Build Procedure
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CROSS_COMPILE=aarch64-linux-gnu- make PLAT=<Target_SoC> bl31
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Target_SoC should be "imx8mq" for i.MX8MQ SoC.
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Target_SoC should be "imx8mm" for i.MX8MM SoC.
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Deploy TF-A Images
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-----------------
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@ -0,0 +1,91 @@
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/*
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* Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <stdlib.h>
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#include <stdint.h>
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#include <stdbool.h>
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#include <common/debug.h>
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#include <drivers/delay_timer.h>
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#include <lib/mmio.h>
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#include <lib/psci/psci.h>
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#include <lib/smccc.h>
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#include <platform_def.h>
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#include <services/std_svc.h>
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#include <gpc.h>
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#include <imx_sip_svc.h>
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void imx_gpc_init(void)
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{
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unsigned int val;
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int i;
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/* mask all the wakeup irq by default */
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for (i = 0; i < 4; i++) {
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mmio_write_32(IMX_GPC_BASE + IMR1_CORE0_A53 + i * 4, ~0x0);
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mmio_write_32(IMX_GPC_BASE + IMR1_CORE1_A53 + i * 4, ~0x0);
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mmio_write_32(IMX_GPC_BASE + IMR1_CORE2_A53 + i * 4, ~0x0);
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mmio_write_32(IMX_GPC_BASE + IMR1_CORE3_A53 + i * 4, ~0x0);
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mmio_write_32(IMX_GPC_BASE + IMR1_CORE0_M4 + i * 4, ~0x0);
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}
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val = mmio_read_32(IMX_GPC_BASE + LPCR_A53_BSC);
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/* use GIC wake_request to wakeup C0~C3 from LPM */
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val |= 0x30c00000;
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/* clear the MASTER0 LPM handshake */
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val &= ~(1 << 6);
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mmio_write_32(IMX_GPC_BASE + LPCR_A53_BSC, val);
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/* clear MASTER1 & MASTER2 mapping in CPU0(A53) */
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mmio_clrbits_32(IMX_GPC_BASE + MST_CPU_MAPPING, (MASTER1_MAPPING |
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MASTER2_MAPPING));
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/* set all mix/PU in A53 domain */
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mmio_write_32(IMX_GPC_BASE + PGC_CPU_0_1_MAPPING, 0xffff);
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/*
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* Set the CORE & SCU power up timing:
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* SW = 0x1, SW2ISO = 0x1;
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* the CPU CORE and SCU power up timming counter
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* is drived by 32K OSC, each domain's power up
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* latency is (SW + SW2ISO) / 32768
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*/
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mmio_write_32(IMX_GPC_BASE + COREx_PGC_PCR(0) + 0x4, 0x81);
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mmio_write_32(IMX_GPC_BASE + COREx_PGC_PCR(1) + 0x4, 0x81);
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mmio_write_32(IMX_GPC_BASE + COREx_PGC_PCR(2) + 0x4, 0x81);
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mmio_write_32(IMX_GPC_BASE + COREx_PGC_PCR(3) + 0x4, 0x81);
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mmio_write_32(IMX_GPC_BASE + PLAT_PGC_PCR + 0x4, 0x81);
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mmio_write_32(IMX_GPC_BASE + PGC_SCU_TIMING,
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(0x59 << 10) | 0x5B | (0x2 << 20));
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/* set DUMMY PDN/PUP ACK by default for A53 domain */
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mmio_write_32(IMX_GPC_BASE + PGC_ACK_SEL_A53,
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A53_DUMMY_PUP_ACK | A53_DUMMY_PDN_ACK);
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/* clear DSM by default */
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val = mmio_read_32(IMX_GPC_BASE + SLPCR);
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val &= ~SLPCR_EN_DSM;
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/* enable the fast wakeup wait mode */
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val |= SLPCR_A53_FASTWUP_WAIT_MODE;
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/* clear the RBC */
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val &= ~(0x3f << SLPCR_RBC_COUNT_SHIFT);
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/* set the STBY_COUNT to 0x5, (128 * 30)us */
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val &= ~(0x7 << SLPCR_STBY_COUNT_SHFT);
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val |= (0x5 << SLPCR_STBY_COUNT_SHFT);
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mmio_write_32(IMX_GPC_BASE + SLPCR, val);
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/*
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* USB PHY power up needs to make sure RESET bit in SRC is clear,
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* otherwise, the PU power up bit in GPC will NOT self-cleared.
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* only need to do it once.
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*/
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mmio_clrbits_32(IMX_SRC_BASE + SRC_OTG1PHY_SCR, 0x1);
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mmio_clrbits_32(IMX_SRC_BASE + SRC_OTG2PHY_SCR, 0x1);
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/* enable all the power domain by default */
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mmio_write_32(IMX_GPC_BASE + PU_PGC_UP_TRG, 0x3fcf);
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}
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@ -0,0 +1,146 @@
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/*
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* Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <assert.h>
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#include <stdbool.h>
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#include <platform_def.h>
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#include <arch_helpers.h>
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#include <common/bl_common.h>
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#include <common/debug.h>
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#include <context.h>
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#include <drivers/arm/tzc380.h>
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#include <drivers/console.h>
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#include <drivers/generic_delay_timer.h>
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#include <lib/el3_runtime/context_mgmt.h>
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#include <lib/mmio.h>
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#include <lib/xlat_tables/xlat_tables.h>
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#include <plat/common/platform.h>
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#include <gpc.h>
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#include <imx_uart.h>
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#include <plat_imx8.h>
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static const mmap_region_t imx_mmap[] = {
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MAP_REGION_FLAT(IMX_GIC_BASE, IMX_GIC_SIZE, MT_DEVICE | MT_RW),
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MAP_REGION_FLAT(IMX_AIPS_BASE, IMX_AIPS_SIZE, MT_DEVICE | MT_RW), /* AIPS map */
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{0},
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};
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static entry_point_info_t bl32_image_ep_info;
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static entry_point_info_t bl33_image_ep_info;
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/* get SPSR for BL33 entry */
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static uint32_t get_spsr_for_bl33_entry(void)
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{
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unsigned long el_status;
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unsigned long mode;
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uint32_t spsr;
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/* figure out what mode we enter the non-secure world */
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el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT;
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el_status &= ID_AA64PFR0_ELX_MASK;
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mode = (el_status) ? MODE_EL2 : MODE_EL1;
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spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS);
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return spsr;
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}
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void bl31_tzc380_setup(void)
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{
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unsigned int val;
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val = mmio_read_32(IMX_IOMUX_GPR_BASE + 0x28);
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if ((val & GPR_TZASC_EN) != GPR_TZASC_EN)
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return;
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tzc380_init(IMX_TZASC_BASE);
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/*
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* Need to substact offset 0x40000000 from CPU address when
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* programming tzasc region for i.mx8mm.
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*/
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/* Enable 1G-5G S/NS RW */
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tzc380_configure_region(0, 0x00000000, TZC_ATTR_REGION_SIZE(TZC_REGION_SIZE_4G) |
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TZC_ATTR_REGION_EN_MASK | TZC_ATTR_SP_ALL);
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}
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void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
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u_register_t arg2, u_register_t arg3)
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{
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static console_uart_t console;
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int i;
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/* Enable CSU NS access permission */
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for (i = 0; i < 64; i++) {
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mmio_write_32(IMX_CSU_BASE + i * 4, 0x00ff00ff);
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}
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console_imx_uart_register(IMX_BOOT_UART_BASE, IMX_BOOT_UART_CLK_IN_HZ,
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IMX_CONSOLE_BAUDRATE, &console);
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/* This console is only used for boot stage */
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console_set_scope(&console.console, CONSOLE_FLAG_BOOT);
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/*
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* tell BL3-1 where the non-secure software image is located
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* and the entry state information.
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*/
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bl33_image_ep_info.pc = PLAT_NS_IMAGE_OFFSET;
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bl33_image_ep_info.spsr = get_spsr_for_bl33_entry();
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SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE);
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bl31_tzc380_setup();
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}
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void bl31_plat_arch_setup(void)
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{
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mmap_add_region(BL31_BASE, BL31_BASE, (BL31_LIMIT - BL31_BASE),
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MT_MEMORY | MT_RW | MT_SECURE);
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mmap_add_region(BL_CODE_BASE, BL_CODE_BASE, (BL_CODE_END - BL_CODE_BASE),
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MT_MEMORY | MT_RO | MT_SECURE);
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#if USE_COHERENT_MEM
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mmap_add_region(BL_COHERENT_RAM_BASE, BL_COHERENT_RAM_BASE,
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(BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE),
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MT_DEVICE | MT_RW | MT_SECURE);
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#endif
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mmap_add(imx_mmap);
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init_xlat_tables();
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enable_mmu_el3(0);
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}
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void bl31_platform_setup(void)
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{
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generic_delay_timer_init();
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/* select the CKIL source to 32K OSC */
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mmio_write_32(IMX_ANAMIX_BASE + ANAMIX_MISC_CTL, 0x1);
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plat_gic_driver_init();
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plat_gic_init();
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imx_gpc_init();
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}
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entry_point_info_t *bl31_plat_get_next_image_ep_info(unsigned int type)
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{
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if (type == NON_SECURE)
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return &bl33_image_ep_info;
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if (type == SECURE)
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return &bl32_image_ep_info;
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return NULL;
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}
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unsigned int plat_get_syscnt_freq2(void)
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{
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return COUNTER_FREQUENCY;
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}
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@ -0,0 +1,44 @@
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/*
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* Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <stdbool.h>
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#include <arch.h>
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#include <arch_helpers.h>
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#include <common/debug.h>
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#include <lib/mmio.h>
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#include <lib/psci/psci.h>
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#include <gpc.h>
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#include <imx8m_psci.h>
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#include <plat_imx8.h>
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static const plat_psci_ops_t imx_plat_psci_ops = {
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.pwr_domain_on = imx_pwr_domain_on,
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.pwr_domain_on_finish = imx_pwr_domain_on_finish,
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.pwr_domain_off = imx_pwr_domain_off,
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.validate_ns_entrypoint = imx_validate_ns_entrypoint,
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.validate_power_state = imx_validate_power_state,
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.cpu_standby = imx_cpu_standby,
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.pwr_domain_suspend = imx_domain_suspend,
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.pwr_domain_suspend_finish = imx_domain_suspend_finish,
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.pwr_domain_pwr_down_wfi = imx_pwr_domain_pwr_down_wfi,
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.get_sys_suspend_power_state = imx_get_sys_suspend_power_state,
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.system_reset = imx_system_reset,
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.system_off = imx_system_off,
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};
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/* export the platform specific psci ops */
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int plat_setup_psci_ops(uintptr_t sec_entrypoint,
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const plat_psci_ops_t **psci_ops)
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{
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/* sec_entrypoint is used for warm reset */
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imx_mailbox_init(sec_entrypoint);
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*psci_ops = &imx_plat_psci_ops;
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return 0;
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}
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/*
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* Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#define PLATFORM_LINKER_FORMAT "elf64-littleaarch64"
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#define PLATFORM_LINKER_ARCH aarch64
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#define PLATFORM_STACK_SIZE 0xB00
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#define CACHE_WRITEBACK_GRANULE 64
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#define PLAT_PRIMARY_CPU 0x0
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#define PLATFORM_MAX_CPU_PER_CLUSTER 4
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#define PLATFORM_CLUSTER_COUNT 1
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#define PLATFORM_CLUSTER0_CORE_COUNT 4
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#define PLATFORM_CLUSTER1_CORE_COUNT 0
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#define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER0_CORE_COUNT)
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#define IMX_PWR_LVL0 MPIDR_AFFLVL0
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#define IMX_PWR_LVL1 MPIDR_AFFLVL1
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#define IMX_PWR_LVL2 MPIDR_AFFLVL2
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#define PWR_DOMAIN_AT_MAX_LVL U(1)
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#define PLAT_MAX_PWR_LVL U(2)
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#define PLAT_MAX_OFF_STATE U(4)
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#define PLAT_MAX_RET_STATE U(2)
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#define PLAT_WAIT_RET_STATE U(1)
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#define PLAT_STOP_OFF_STATE U(3)
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#define BL31_BASE U(0x920000)
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#define BL31_LIMIT U(0x940000)
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#define BL32_BASE U(0xbe000000)
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/* non-secure uboot base */
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#define PLAT_NS_IMAGE_OFFSET U(0x40200000)
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/* GICv3 base address */
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#define PLAT_GICD_BASE U(0x38800000)
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#define PLAT_GICR_BASE U(0x38880000)
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#define PLAT_VIRT_ADDR_SPACE_SIZE (1ull << 32)
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#define PLAT_PHY_ADDR_SPACE_SIZE (1ull << 32)
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#define MAX_XLAT_TABLES 8
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#define MAX_MMAP_REGIONS 16
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#define HAB_RVT_BASE U(0x00000900) /* HAB_RVT for i.MX8MM */
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#define IMX_BOOT_UART_BASE U(0x30890000)
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#define IMX_BOOT_UART_CLK_IN_HZ 24000000 /* Select 24MHz oscillator */
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#define PLAT_CRASH_UART_BASE IMX_BOOT_UART_BASE
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#define PLAT_CRASH_UART_CLK_IN_HZ 24000000
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#define IMX_CONSOLE_BAUDRATE 115200
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#define IMX_AIPSTZ1 U(0x301f0000)
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#define IMX_AIPSTZ2 U(0x305f0000)
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#define IMX_AIPSTZ3 U(0x309f0000)
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#define IMX_AIPSTZ4 U(0x32df0000)
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#define IMX_AIPS_BASE U(0x30000000)
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#define IMX_AIPS_SIZE U(0xC00000)
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#define IMX_GPV_BASE U(0x32000000)
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#define IMX_GPV_SIZE U(0x800000)
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#define IMX_AIPS1_BASE U(0x30200000)
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#define IMX_AIPS4_BASE U(0x32c00000)
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#define IMX_ANAMIX_BASE U(0x30360000)
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#define IMX_CCM_BASE U(0x30380000)
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#define IMX_SRC_BASE U(0x30390000)
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#define IMX_GPC_BASE U(0x303a0000)
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#define IMX_RDC_BASE U(0x303d0000)
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#define IMX_CSU_BASE U(0x303e0000)
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#define IMX_WDOG_BASE U(0x30280000)
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#define IMX_SNVS_BASE U(0x30370000)
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#define IMX_NOC_BASE U(0x32700000)
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#define IMX_TZASC_BASE U(0x32F80000)
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#define IMX_IOMUX_GPR_BASE U(0x30340000)
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#define IMX_DDRC_BASE U(0x3d400000)
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#define IMX_DDRPHY_BASE U(0x3c000000)
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#define IMX_DDR_IPS_BASE U(0x3d000000)
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#define IMX_ROM_BASE U(0x0)
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#define GPV_BASE U(0x32000000)
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#define GPV_SIZE U(0x800000)
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#define IMX_GIC_BASE PLAT_GICD_BASE
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#define IMX_GIC_SIZE U(0x200000)
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#define WDOG_WSR U(0x2)
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#define WDOG_WCR_WDZST BIT(0)
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#define WDOG_WCR_WDBG BIT(1)
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#define WDOG_WCR_WDE BIT(2)
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#define WDOG_WCR_WDT BIT(3)
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#define WDOG_WCR_SRS BIT(4)
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#define WDOG_WCR_WDA BIT(5)
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#define WDOG_WCR_SRE BIT(6)
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#define WDOG_WCR_WDW BIT(7)
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#define SRC_A53RCR0 U(0x4)
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#define SRC_A53RCR1 U(0x8)
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#define SRC_OTG1PHY_SCR U(0x20)
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#define SRC_OTG2PHY_SCR U(0x24)
|
||||
#define SRC_GPR1_OFFSET U(0x74)
|
||||
|
||||
#define SNVS_LPCR U(0x38)
|
||||
#define SNVS_LPCR_SRTC_ENV BIT(0)
|
||||
#define SNVS_LPCR_DP_EN BIT(5)
|
||||
#define SNVS_LPCR_TOP BIT(6)
|
||||
|
||||
#define IOMUXC_GPR10 U(0x28)
|
||||
#define GPR_TZASC_EN BIT(0)
|
||||
#define GPR_TZASC_EN_LOCK BIT(16)
|
||||
|
||||
#define ANAMIX_MISC_CTL U(0x124)
|
||||
|
||||
#define MAX_CSU_NUM U(64)
|
||||
|
||||
#define OCRAM_S_BASE U(0x00180000)
|
||||
#define OCRAM_S_SIZE U(0x8000)
|
||||
#define OCRAM_S_LIMIT (OCRAM_S_BASE + OCRAM_S_SIZE)
|
||||
|
||||
#define COUNTER_FREQUENCY 8000000 /* 8MHz */
|
||||
|
||||
#define IMX_WDOG_B_RESET
|
||||
|
|
@ -0,0 +1,44 @@
|
|||
#
|
||||
# Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
|
||||
#
|
||||
# SPDX-License-Identifier: BSD-3-Clause
|
||||
#
|
||||
|
||||
PLAT_INCLUDES := -Iplat/imx/common/include \
|
||||
-Iplat/imx/imx8m/include \
|
||||
-Iplat/imx/imx8m/imx8mm/include
|
||||
|
||||
IMX_GIC_SOURCES := drivers/arm/gic/v3/gicv3_helpers.c \
|
||||
drivers/arm/gic/v3/arm_gicv3_common.c \
|
||||
drivers/arm/gic/v3/gic500.c \
|
||||
drivers/arm/gic/v3/gicv3_main.c \
|
||||
drivers/arm/gic/common/gic_common.c \
|
||||
plat/common/plat_gicv3.c \
|
||||
plat/common/plat_psci_common.c \
|
||||
plat/imx/common/plat_imx8_gic.c
|
||||
|
||||
BL31_SOURCES += plat/imx/common/imx8_helpers.S \
|
||||
plat/imx/imx8m/gpc_common.c \
|
||||
plat/imx/imx8m/imx8m_psci_common.c \
|
||||
plat/imx/imx8m/imx8mm/imx8mm_bl31_setup.c \
|
||||
plat/imx/imx8m/imx8mm/imx8mm_psci.c \
|
||||
plat/imx/imx8m/imx8mm/gpc.c \
|
||||
plat/imx/common/imx8_topology.c \
|
||||
plat/imx/common/imx_uart_console.S \
|
||||
lib/xlat_tables/aarch64/xlat_tables.c \
|
||||
lib/xlat_tables/xlat_tables_common.c \
|
||||
lib/cpus/aarch64/cortex_a53.S \
|
||||
drivers/console/aarch64/console.S \
|
||||
drivers/arm/tzc/tzc380.c \
|
||||
drivers/delay_timer/delay_timer.c \
|
||||
drivers/delay_timer/generic_delay_timer.c \
|
||||
${IMX_GIC_SOURCES}
|
||||
|
||||
USE_COHERENT_MEM := 1
|
||||
RESET_TO_BL31 := 1
|
||||
A53_DISABLE_NON_TEMPORAL_HINT := 0
|
||||
MULTI_CONSOLE_API := 1
|
||||
|
||||
ERRATA_A53_835769 := 1
|
||||
ERRATA_A53_843419 := 1
|
||||
ERRATA_A53_855873 := 1
|
||||
|
|
@ -68,6 +68,9 @@
|
|||
#define SLT_PLAT_PDN BIT(8)
|
||||
#define SLT_PLAT_PUP BIT(9)
|
||||
|
||||
#define MASTER1_MAPPING BIT(1)
|
||||
#define MASTER2_MAPPING BIT(2)
|
||||
|
||||
/* helper macro */
|
||||
#define A53_LPM_MASK U(0xF)
|
||||
#define A53_LPM_WAIT U(0x5)
|
||||
|
|
|
|||
Loading…
Reference in New Issue