ti: k3: Setup initial files for platform
Create the baseline Makefile, platform definitions file and platform specific assembly macros file. This includes first set of constants for the platform including cache sizes and linker format and a stub for BL31 and the basic memory layout K3 SoC family of processors do not use require a BL1 or BL2 binary, since such functions are provided by an system controller on the SoC. This lowers the burden of ATF to purely managing the local ARM cores themselves. Signed-off-by: Benjamin Fair <b-fair@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Signed-off-by: Andrew F. Davis <afd@ti.com>
This commit is contained in:
Nishanth Menon
Andrew F. Davis
parent
d135ad7884
commit
1841c533c9
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@ -0,0 +1,55 @@
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Trusted Firmware-A for Texas Instruments K3 SoCs
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================================================
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Trusted Firmware-A (TF-A) implements the EL3 firmware layer for Texas Instruments K3 SoCs.
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Boot Flow
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---------
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R5(U-Boot) --> TF-A BL31 --> BL32(OP-TEE) --> TF-A BL31 --> BL33(U-Boot) --> Linux
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\
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Optional direct to Linux boot
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\
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--> BL33(Linux)
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Texas Instruments K3 SoCs contain an R5 processor used as the boot master, it
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loads the needed images for A53 startup, because of this we do not need BL1 or
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BL2 TF-A stages.
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Build Instructions
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------------------
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https://github.com/ARM-software/arm-trusted-firmware.git
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TF-A:
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.. code:: shell
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make CROSS_COMPILE=aarch64-linux-gnu- PLAT=k3 SPD=opteed all
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OP-TEE:
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.. code:: shell
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make ARCH=arm CROSS_COMPILE64=aarch64-linux-gnu- PLATFORM=k3 CFG_ARM64_core=y all
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R5 U-Boot:
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.. code:: shell
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make ARCH=arm CROSS_COMPILE=arm-linux-gnueabihf- am65x_evm_r5_defconfig
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make ARCH=arm CROSS_COMPILE=arm-linux-gnueabihf- SYSFW=<path to SYSFW>
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A53 U-Boot:
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.. code:: shell
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make ARCH=arm CROSS_COMPILE=aarch64-linux-gnu- am65x_evm_a53_defconfig
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make ARCH=arm CROSS_COMPILE=aarch64-linux-gnu- ATF=<path> TEE=<path>
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Deploy Images
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-------------
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.. code:: shell
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cp tiboot3.bin tispl.bin u-boot.img /sdcard/boot/
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@ -132,6 +132,16 @@ Files:
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- plat/rockchip/\*
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Texas Instruments platform sub-maintainer
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-----------------------------------------
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Andrew F. Davis (afd@ti.com, `glneo`_)
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Files:
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- docs/plat/ti-k3.rst
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- plat/ti/\*
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UniPhier platform sub-maintainer
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--------------------------------
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@ -167,6 +177,7 @@ Etienne Carriere (etienne.carriere@linaro.org, `etienne-lms`_)
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.. _masahir0y: https://github.com/masahir0y
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.. _mtk09422: https://github.com/mtk09422
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.. _TonyXie06: https://github.com/TonyXie06
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.. _glneo: https://github.com/glneo
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.. _sivadur: https://github.com/sivadur
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.. _rockchip-linux: https://github.com/rockchip-linux
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.. _etienne-lms: https://github.com/etienne-lms
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/*
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* Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <arch_helpers.h>
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#include <assert.h>
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#include <bl_common.h>
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#include <debug.h>
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#include <platform_def.h>
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#include <string.h>
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/*******************************************************************************
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* Perform any BL3-1 early platform setup, such as console init and deciding on
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* memory layout.
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******************************************************************************/
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void bl31_early_platform_setup(bl31_params_t *from_bl2,
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void *plat_params_from_bl2)
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{
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/* There are no parameters from BL2 if BL31 is a reset vector */
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assert(from_bl2 == NULL);
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assert(plat_params_from_bl2 == NULL);
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}
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void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
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u_register_t arg2, u_register_t arg3)
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{
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bl31_early_platform_setup((void *)arg0, (void *)arg1);
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}
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void bl31_plat_arch_setup(void)
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{
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/* TODO: Initialize the MMU tables */
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}
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void bl31_platform_setup(void)
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{
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/* TODO: Initialize the GIC CPU and distributor interfaces */
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}
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void platform_mem_init(void)
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{
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/* Do nothing for now... */
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}
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/*
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* Empty function to prevent the console from being uninitialized after BL33 is
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* started and allow us to see messages from BL31.
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*/
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void bl31_plat_runtime_setup(void)
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{
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}
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/*******************************************************************************
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* Return a pointer to the 'entry_point_info' structure of the next image
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* for the security state specified. BL3-3 corresponds to the non-secure
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* image type while BL3-2 corresponds to the secure image type. A NULL
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* pointer is returned if the image does not exist.
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******************************************************************************/
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entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type)
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{
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return NULL;
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}
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@ -0,0 +1,37 @@
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#
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# Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
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#
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# SPDX-License-Identifier: BSD-3-Clause
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#
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# We don't use BL1 or BL2, so BL31 is the first image to execute
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RESET_TO_BL31 := 1
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# Only one core starts up at first
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COLD_BOOT_SINGLE_CPU := 1
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# We can choose where a core starts executing
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PROGRAMMABLE_RESET_ADDRESS:= 1
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# System coherency is managed in hardware
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HW_ASSISTED_COHERENCY := 1
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USE_COHERENT_MEM := 0
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ERROR_DEPRECATED := 1
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ENABLE_PLAT_COMPAT := 0
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# A53 erratum for SoC. (enable them all)
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ERRATA_A53_826319 := 1
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ERRATA_A53_835769 := 1
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ERRATA_A53_836870 := 1
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ERRATA_A53_843419 := 1
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ERRATA_A53_855873 := 1
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PLAT_INCLUDES += \
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-I${PLAT_PATH}/include \
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-Iinclude/plat/arm/common/ \
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-Iinclude/plat/arm/common/aarch64/ \
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PLAT_BL_COMMON_SOURCES += \
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lib/cpus/aarch64/cortex_a53.S \
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BL31_SOURCES += \
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${PLAT_PATH}/common/k3_bl31_setup.c \
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/*
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* Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef __PLAT_MACROS_S__
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#define __PLAT_MACROS_S__
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/* ---------------------------------------------
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* The below required platform porting macro
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* prints out relevant platform registers
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* whenever an unhandled exception is taken in
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* BL31.
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* ---------------------------------------------
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*/
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.macro plat_crash_print_regs
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/* STUB */
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.endm
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#endif /* __PLAT_MACROS_S__ */
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/*
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* Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef __PLATFORM_DEF_H__
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#define __PLATFORM_DEF_H__
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#include <arch.h>
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#include <board_def.h>
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#include <common_def.h>
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/*******************************************************************************
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* Generic platform constants
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******************************************************************************/
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/* Size of cacheable stack */
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#if IMAGE_BL31
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#define PLATFORM_STACK_SIZE 0x800
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#else
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#define PLATFORM_STACK_SIZE 0x1000
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#endif
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#define PLAT_NUM_PWR_DOMAINS (PLATFORM_CLUSTER_COUNT + \
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PLATFORM_CORE_COUNT)
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#define PLAT_MAX_PWR_LVL MPIDR_AFFLVL1
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/*******************************************************************************
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* Memory layout constants
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******************************************************************************/
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/*
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* ARM-TF lives in SRAM, partition it here
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*/
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#define SHARED_RAM_BASE BL31_LIMIT
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#define SHARED_RAM_SIZE 0x00001000
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/*
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* BL3-1 specific defines.
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*
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* Put BL3-1 at the base of the Trusted SRAM, before SHARED_RAM.
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*/
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#define BL31_BASE SEC_SRAM_BASE
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#define BL31_SIZE (SEC_SRAM_SIZE - SHARED_RAM_SIZE)
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#define BL31_LIMIT (BL31_BASE + BL31_SIZE)
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#define BL31_PROGBITS_LIMIT BL31_LIMIT
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/*
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* Some data must be aligned on the biggest cache line size in the platform.
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* This is known only to the platform as it might have a combination of
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* integrated and external caches.
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*/
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#define CACHE_WRITEBACK_SHIFT 6
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#define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT)
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#endif /* __PLATFORM_DEF_H__ */
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#
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# Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
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#
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# SPDX-License-Identifier: BSD-3-Clause
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#
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PLAT_PATH := plat/ti/k3
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include ${PLAT_PATH}/common/plat_common.mk
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# modify BUILD_PLAT to point to board specific build directory
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BUILD_PLAT := ${BUILD_BASE}/${PLAT}/${TARGET_BOARD}/${BUILD_TYPE}
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@ -183,6 +183,7 @@ This release also contains the following platform support:
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- Raspberry Pi 3 board
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- RockChip RK3328, RK3368 and RK3399 SoCs
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- Socionext UniPhier SoC family
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- Texas Instruments K3 SoCs
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- Xilinx Zynq UltraScale + MPSoC
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Still to come
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