diff --git a/bl1/aarch64/bl1_arch_setup.c b/bl1/aarch64/bl1_arch_setup.c index a1ebbdb20..5725bac12 100644 --- a/bl1/aarch64/bl1_arch_setup.c +++ b/bl1/aarch64/bl1_arch_setup.c @@ -39,10 +39,9 @@ void bl1_arch_setup(void) { unsigned long tmp_reg = 0; - /* Enable alignment checks and set the exception endianess to LE */ + /* Enable alignment checks */ tmp_reg = read_sctlr_el3(); tmp_reg |= (SCTLR_A_BIT | SCTLR_SA_BIT); - tmp_reg &= ~SCTLR_EE_BIT; write_sctlr_el3(tmp_reg); isb(); diff --git a/bl1/aarch64/bl1_entrypoint.S b/bl1/aarch64/bl1_entrypoint.S index c081af48f..7259601d1 100644 --- a/bl1/aarch64/bl1_entrypoint.S +++ b/bl1/aarch64/bl1_entrypoint.S @@ -42,6 +42,16 @@ */ func bl1_entrypoint + /* --------------------------------------------- + * Set the CPU endianness before doing anything + * that might involve memory reads or writes + * --------------------------------------------- + */ + mrs x0, sctlr_el3 + bic x0, x0, #SCTLR_EE_BIT + msr sctlr_el3, x0 + isb + /* --------------------------------------------- * Perform any processor specific actions upon * reset e.g. cache, tlb invalidations etc. diff --git a/bl31/aarch64/bl31_arch_setup.c b/bl31/aarch64/bl31_arch_setup.c index acaa6b571..ad73de022 100644 --- a/bl31/aarch64/bl31_arch_setup.c +++ b/bl31/aarch64/bl31_arch_setup.c @@ -45,10 +45,9 @@ void bl31_arch_setup(void) unsigned long tmp_reg = 0; uint64_t counter_freq; - /* Enable alignment checks and set the exception endianness to LE */ + /* Enable alignment checks */ tmp_reg = read_sctlr_el3(); tmp_reg |= (SCTLR_A_BIT | SCTLR_SA_BIT); - tmp_reg &= ~SCTLR_EE_BIT; write_sctlr_el3(tmp_reg); /*