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Merge pull request #1714 from chandnich/sgiclark-helios 

SGI-Clark.Helios platform support patches
This commit is contained in:
Soby Mathew 2018-12-11 10:53:36 +00:00 committed by GitHub
parent 74203d268e a46cdc0533
commit 19122fcada
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GPG Key ID: 4AEE18F83AFDEB23
9 changed files with 214 additions and 1 deletions
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22
plat/arm/board/sgiclarkh/fdts/sgiclarkh_nt_fw_config.dts Normal file
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@ -0,0 +1,22 @@
/*
* Copyright (c) 2018, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/dts-v1/;
/ {
/* compatible string */
compatible = "arm,sgi-clark";
/*
* Place holder for system-id node with default values. The
* value of platform-id and config-id will be set to the
* correct values during the BL2 stage of boot.
*/
system-id {
platform-id = <0x0>;
config-id = <0x0>;
};
};

25
plat/arm/board/sgiclarkh/fdts/sgiclarkh_tb_fw_config.dts Normal file
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@ -0,0 +1,25 @@
/*
* Copyright (c) 2018, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/dts-v1/;
/ {
/* Platform Config */
compatible = "arm,tb_fw";
nt_fw_config_addr = <0x0 0xFEF00000>;
nt_fw_config_max_size = <0x0100000>;
/*
* The following two entries are placeholders for Mbed TLS
* heap information. The default values don't matter since
* they will be overwritten by BL1.
* In case of having shared Mbed TLS heap between BL1 and BL2,
* BL1 will populate these two properties with the respective
* info about the shared heap. This info will be available for
* BL2 in order to locate and re-use the heap.
*/
mbedtls_heap_addr = <0x0 0x0>;
mbedtls_heap_size = <0x0>;
};

27
plat/arm/board/sgiclarkh/include/platform_def.h Normal file
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@ -0,0 +1,27 @@
/*
* Copyright (c) 2018, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef PLATFORM_DEF_H
#define PLATFORM_DEF_H
#include <sgi_base_platform_def.h>
#include <utils_def.h>
#define PLAT_ARM_CLUSTER_COUNT 2
#define CSS_SGI_MAX_CPUS_PER_CLUSTER 8
#define CSS_SGI_MAX_PE_PER_CPU 2
#define PLAT_CSS_MHU_BASE UL(0x45400000)
/* Base address of DMC-620 instances */
#define SGICLARKH_DMC620_BASE0 UL(0x4e000000)
#define SGICLARKH_DMC620_BASE1 UL(0x4e100000)
#define PLAT_MAX_PWR_LVL ARM_PWR_LVL2
#define CSS_SYSTEM_PWR_DMN_LVL ARM_PWR_LVL3
#endif /* PLATFORM_DEF_H */

42
plat/arm/board/sgiclarkh/platform.mk Normal file
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@ -0,0 +1,42 @@
#
# Copyright (c) 2018, Arm Limited. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
include plat/arm/css/sgi/sgi-common.mk
SGICLARKH_BASE = plat/arm/board/sgiclarkh
PLAT_INCLUDES += -I${SGICLARKH_BASE}/include/
SGI_CPU_SOURCES := lib/cpus/aarch64/cortex_helios.S
BL1_SOURCES += ${SGI_CPU_SOURCES}
BL2_SOURCES += ${SGICLARKH_BASE}/sgiclarkh_plat.c \
${SGICLARKH_BASE}/sgiclarkh_security.c \
drivers/arm/tzc/tzc_dmc620.c \
lib/utils/mem_region.c \
plat/arm/common/arm_nor_psci_mem_protect.c
BL31_SOURCES += ${SGI_CPU_SOURCES} \
${SGICLARKH_BASE}/sgiclarkh_plat.c \
drivers/cfi/v2m/v2m_flash.c \
lib/utils/mem_region.c \
plat/arm/common/arm_nor_psci_mem_protect.c
# Add the FDT_SOURCES and options for Dynamic Config
FDT_SOURCES += ${SGICLARKH_BASE}/fdts/${PLAT}_tb_fw_config.dts
TB_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_tb_fw_config.dtb
# Add the TB_FW_CONFIG to FIP and specify the same to certtool
$(eval $(call TOOL_ADD_PAYLOAD,${TB_FW_CONFIG},--tb-fw-config))
FDT_SOURCES += ${SGICLARKH_BASE}/fdts/${PLAT}_nt_fw_config.dts
NT_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_nt_fw_config.dtb
# Add the NT_FW_CONFIG to FIP and specify the same to certtool
$(eval $(call TOOL_ADD_PAYLOAD,${NT_FW_CONFIG},--nt-fw-config))
override CTX_INCLUDE_AARCH32_REGS := 0

18
plat/arm/board/sgiclarkh/sgiclarkh_plat.c Normal file
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@ -0,0 +1,18 @@
/*
* Copyright (c) 2018, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <platform.h>
unsigned int plat_arm_sgi_get_platform_id(void)
{
return mmio_read_32(SID_REG_BASE + SID_SYSTEM_ID_OFFSET)
& SID_SYSTEM_ID_PART_NUM_MASK;
}
unsigned int plat_arm_sgi_get_config_id(void)
{
return mmio_read_32(SID_REG_BASE + SID_SYSTEM_CFG_OFFSET);
}

39
plat/arm/board/sgiclarkh/sgiclarkh_security.c Normal file
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@ -0,0 +1,39 @@
/*
* Copyright (c) 2018, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <debug.h>
#include <platform_def.h>
#include <tzc_dmc620.h>
uintptr_t sgiclarkh_dmc_base[] = {
SGICLARKH_DMC620_BASE0,
SGICLARKH_DMC620_BASE1
};
static const tzc_dmc620_driver_data_t sgiclarkh_plat_driver_data = {
.dmc_base = sgiclarkh_dmc_base,
.dmc_count = ARRAY_SIZE(sgiclarkh_dmc_base)
};
static const tzc_dmc620_acc_addr_data_t sgiclarkh_acc_addr_data[] = {
{
.region_base = ARM_AP_TZC_DRAM1_BASE,
.region_top = ARM_AP_TZC_DRAM1_BASE + ARM_TZC_DRAM1_SIZE - 1,
.sec_attr = TZC_DMC620_REGION_S_RDWR
}
};
static const tzc_dmc620_config_data_t sgiclarkh_plat_config_data = {
.plat_drv_data = &sgiclarkh_plat_driver_data,
.plat_acc_addr_data = sgiclarkh_acc_addr_data,
.acc_addr_count = ARRAY_SIZE(sgiclarkh_acc_addr_data)
};
/* Initialize the secure environment */
void plat_arm_security_setup(void)
{
arm_tzc_dmc620_setup(&sgiclarkh_plat_config_data);
}

1
plat/arm/css/sgi/include/sgi_variant.h
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@ -12,6 +12,7 @@
/* SID Version values for SGI-Clark */
#define SGI_CLARK_SID_VER_PART_NUM 0x0786
#define SGI_CLARK_HELIOS_CONFIG_ID 0x2
/* Structure containing SGI platform variant information */
typedef struct sgi_platform_info {

11
plat/arm/css/sgi/sgi_bl31_setup.c
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@ -62,5 +62,16 @@ void bl31_platform_setup(void)
const plat_psci_ops_t *plat_arm_psci_override_pm_ops(plat_psci_ops_t *ops)
{
/* For SGI-Clark.Helios platform only CPU ON/OFF is supported */
if ((sgi_plat_info.platform_id == SGI_CLARK_SID_VER_PART_NUM) &&
(sgi_plat_info.config_id == SGI_CLARK_HELIOS_CONFIG_ID)) {
ops->cpu_standby = NULL;
ops->system_off = NULL;
ops->system_reset = NULL;
ops->get_sys_suspend_power_state = NULL;
ops->pwr_domain_suspend = NULL;
ops->pwr_domain_suspend_finish = NULL;
}
return css_scmi_override_pm_ops(ops);
}

30
plat/arm/css/sgi/sgi_topology.c
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@ -5,6 +5,7 @@
*/
#include <plat_arm.h>
#include <sgi_variant.h>
/* Topology */
/*
@ -19,12 +20,39 @@ const unsigned char sgi_pd_tree_desc[] = {
CSS_SGI_MAX_CPUS_PER_CLUSTER
};
/* SGI-Clark.Helios platform consists of 16 physical CPUS and 32 threads */
const unsigned char sgi_clark_helios_pd_tree_desc[] = {
PLAT_ARM_CLUSTER_COUNT,
CSS_SGI_MAX_CPUS_PER_CLUSTER,
CSS_SGI_MAX_CPUS_PER_CLUSTER,
CSS_SGI_MAX_PE_PER_CPU,
CSS_SGI_MAX_PE_PER_CPU,
CSS_SGI_MAX_PE_PER_CPU,
CSS_SGI_MAX_PE_PER_CPU,
CSS_SGI_MAX_PE_PER_CPU,
CSS_SGI_MAX_PE_PER_CPU,
CSS_SGI_MAX_PE_PER_CPU,
CSS_SGI_MAX_PE_PER_CPU,
CSS_SGI_MAX_PE_PER_CPU,
CSS_SGI_MAX_PE_PER_CPU,
CSS_SGI_MAX_PE_PER_CPU,
CSS_SGI_MAX_PE_PER_CPU,
CSS_SGI_MAX_PE_PER_CPU,
CSS_SGI_MAX_PE_PER_CPU,
CSS_SGI_MAX_PE_PER_CPU,
CSS_SGI_MAX_PE_PER_CPU
};
/*******************************************************************************
* This function returns the topology tree information.
******************************************************************************/
const unsigned char *plat_get_power_domain_tree_desc(void)
{
return sgi_pd_tree_desc;
if (sgi_plat_info.platform_id == SGI_CLARK_SID_VER_PART_NUM &&
sgi_plat_info.config_id == SGI_CLARK_HELIOS_CONFIG_ID)
return sgi_clark_helios_pd_tree_desc;
else
return sgi_pd_tree_desc;
}
/*******************************************************************************