Merge pull request #1714 from chandnich/sgiclark-helios
SGI-Clark.Helios platform support patches
This commit is contained in:
commit
19122fcada
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/*
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* Copyright (c) 2018, Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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/dts-v1/;
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/ {
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/* compatible string */
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compatible = "arm,sgi-clark";
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/*
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* Place holder for system-id node with default values. The
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* value of platform-id and config-id will be set to the
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* correct values during the BL2 stage of boot.
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*/
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system-id {
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platform-id = <0x0>;
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config-id = <0x0>;
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};
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};
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/*
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* Copyright (c) 2018, Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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/dts-v1/;
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/ {
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/* Platform Config */
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compatible = "arm,tb_fw";
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nt_fw_config_addr = <0x0 0xFEF00000>;
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nt_fw_config_max_size = <0x0100000>;
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/*
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* The following two entries are placeholders for Mbed TLS
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* heap information. The default values don't matter since
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* they will be overwritten by BL1.
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* In case of having shared Mbed TLS heap between BL1 and BL2,
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* BL1 will populate these two properties with the respective
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* info about the shared heap. This info will be available for
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* BL2 in order to locate and re-use the heap.
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*/
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mbedtls_heap_addr = <0x0 0x0>;
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mbedtls_heap_size = <0x0>;
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};
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/*
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* Copyright (c) 2018, Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef PLATFORM_DEF_H
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#define PLATFORM_DEF_H
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#include <sgi_base_platform_def.h>
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#include <utils_def.h>
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#define PLAT_ARM_CLUSTER_COUNT 2
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#define CSS_SGI_MAX_CPUS_PER_CLUSTER 8
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#define CSS_SGI_MAX_PE_PER_CPU 2
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#define PLAT_CSS_MHU_BASE UL(0x45400000)
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/* Base address of DMC-620 instances */
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#define SGICLARKH_DMC620_BASE0 UL(0x4e000000)
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#define SGICLARKH_DMC620_BASE1 UL(0x4e100000)
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#define PLAT_MAX_PWR_LVL ARM_PWR_LVL2
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#define CSS_SYSTEM_PWR_DMN_LVL ARM_PWR_LVL3
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#endif /* PLATFORM_DEF_H */
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#
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# Copyright (c) 2018, Arm Limited. All rights reserved.
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#
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# SPDX-License-Identifier: BSD-3-Clause
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#
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include plat/arm/css/sgi/sgi-common.mk
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SGICLARKH_BASE = plat/arm/board/sgiclarkh
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PLAT_INCLUDES += -I${SGICLARKH_BASE}/include/
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SGI_CPU_SOURCES := lib/cpus/aarch64/cortex_helios.S
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BL1_SOURCES += ${SGI_CPU_SOURCES}
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BL2_SOURCES += ${SGICLARKH_BASE}/sgiclarkh_plat.c \
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${SGICLARKH_BASE}/sgiclarkh_security.c \
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drivers/arm/tzc/tzc_dmc620.c \
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lib/utils/mem_region.c \
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plat/arm/common/arm_nor_psci_mem_protect.c
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BL31_SOURCES += ${SGI_CPU_SOURCES} \
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${SGICLARKH_BASE}/sgiclarkh_plat.c \
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drivers/cfi/v2m/v2m_flash.c \
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lib/utils/mem_region.c \
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plat/arm/common/arm_nor_psci_mem_protect.c
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# Add the FDT_SOURCES and options for Dynamic Config
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FDT_SOURCES += ${SGICLARKH_BASE}/fdts/${PLAT}_tb_fw_config.dts
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TB_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_tb_fw_config.dtb
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# Add the TB_FW_CONFIG to FIP and specify the same to certtool
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$(eval $(call TOOL_ADD_PAYLOAD,${TB_FW_CONFIG},--tb-fw-config))
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FDT_SOURCES += ${SGICLARKH_BASE}/fdts/${PLAT}_nt_fw_config.dts
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NT_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_nt_fw_config.dtb
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# Add the NT_FW_CONFIG to FIP and specify the same to certtool
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$(eval $(call TOOL_ADD_PAYLOAD,${NT_FW_CONFIG},--nt-fw-config))
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override CTX_INCLUDE_AARCH32_REGS := 0
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/*
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* Copyright (c) 2018, Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <platform.h>
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unsigned int plat_arm_sgi_get_platform_id(void)
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{
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return mmio_read_32(SID_REG_BASE + SID_SYSTEM_ID_OFFSET)
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& SID_SYSTEM_ID_PART_NUM_MASK;
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}
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unsigned int plat_arm_sgi_get_config_id(void)
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{
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return mmio_read_32(SID_REG_BASE + SID_SYSTEM_CFG_OFFSET);
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}
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/*
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* Copyright (c) 2018, Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <debug.h>
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#include <platform_def.h>
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#include <tzc_dmc620.h>
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uintptr_t sgiclarkh_dmc_base[] = {
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SGICLARKH_DMC620_BASE0,
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SGICLARKH_DMC620_BASE1
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};
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static const tzc_dmc620_driver_data_t sgiclarkh_plat_driver_data = {
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.dmc_base = sgiclarkh_dmc_base,
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.dmc_count = ARRAY_SIZE(sgiclarkh_dmc_base)
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};
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static const tzc_dmc620_acc_addr_data_t sgiclarkh_acc_addr_data[] = {
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{
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.region_base = ARM_AP_TZC_DRAM1_BASE,
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.region_top = ARM_AP_TZC_DRAM1_BASE + ARM_TZC_DRAM1_SIZE - 1,
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.sec_attr = TZC_DMC620_REGION_S_RDWR
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}
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};
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static const tzc_dmc620_config_data_t sgiclarkh_plat_config_data = {
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.plat_drv_data = &sgiclarkh_plat_driver_data,
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.plat_acc_addr_data = sgiclarkh_acc_addr_data,
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.acc_addr_count = ARRAY_SIZE(sgiclarkh_acc_addr_data)
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};
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/* Initialize the secure environment */
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void plat_arm_security_setup(void)
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{
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arm_tzc_dmc620_setup(&sgiclarkh_plat_config_data);
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}
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/* SID Version values for SGI-Clark */
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/* SID Version values for SGI-Clark */
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#define SGI_CLARK_SID_VER_PART_NUM 0x0786
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#define SGI_CLARK_SID_VER_PART_NUM 0x0786
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#define SGI_CLARK_HELIOS_CONFIG_ID 0x2
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/* Structure containing SGI platform variant information */
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/* Structure containing SGI platform variant information */
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typedef struct sgi_platform_info {
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typedef struct sgi_platform_info {
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const plat_psci_ops_t *plat_arm_psci_override_pm_ops(plat_psci_ops_t *ops)
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const plat_psci_ops_t *plat_arm_psci_override_pm_ops(plat_psci_ops_t *ops)
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{
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{
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/* For SGI-Clark.Helios platform only CPU ON/OFF is supported */
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if ((sgi_plat_info.platform_id == SGI_CLARK_SID_VER_PART_NUM) &&
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(sgi_plat_info.config_id == SGI_CLARK_HELIOS_CONFIG_ID)) {
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ops->cpu_standby = NULL;
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ops->system_off = NULL;
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ops->system_reset = NULL;
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ops->get_sys_suspend_power_state = NULL;
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ops->pwr_domain_suspend = NULL;
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ops->pwr_domain_suspend_finish = NULL;
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}
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return css_scmi_override_pm_ops(ops);
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return css_scmi_override_pm_ops(ops);
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}
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}
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*/
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*/
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#include <plat_arm.h>
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#include <plat_arm.h>
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#include <sgi_variant.h>
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/* Topology */
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/* Topology */
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/*
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/*
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CSS_SGI_MAX_CPUS_PER_CLUSTER
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CSS_SGI_MAX_CPUS_PER_CLUSTER
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};
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};
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/* SGI-Clark.Helios platform consists of 16 physical CPUS and 32 threads */
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const unsigned char sgi_clark_helios_pd_tree_desc[] = {
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PLAT_ARM_CLUSTER_COUNT,
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CSS_SGI_MAX_CPUS_PER_CLUSTER,
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CSS_SGI_MAX_CPUS_PER_CLUSTER,
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CSS_SGI_MAX_PE_PER_CPU,
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CSS_SGI_MAX_PE_PER_CPU,
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CSS_SGI_MAX_PE_PER_CPU,
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CSS_SGI_MAX_PE_PER_CPU,
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CSS_SGI_MAX_PE_PER_CPU,
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CSS_SGI_MAX_PE_PER_CPU,
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CSS_SGI_MAX_PE_PER_CPU,
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CSS_SGI_MAX_PE_PER_CPU,
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CSS_SGI_MAX_PE_PER_CPU,
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CSS_SGI_MAX_PE_PER_CPU,
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CSS_SGI_MAX_PE_PER_CPU,
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CSS_SGI_MAX_PE_PER_CPU,
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CSS_SGI_MAX_PE_PER_CPU,
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CSS_SGI_MAX_PE_PER_CPU,
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CSS_SGI_MAX_PE_PER_CPU,
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CSS_SGI_MAX_PE_PER_CPU
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};
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/*******************************************************************************
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/*******************************************************************************
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* This function returns the topology tree information.
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* This function returns the topology tree information.
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******************************************************************************/
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******************************************************************************/
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const unsigned char *plat_get_power_domain_tree_desc(void)
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const unsigned char *plat_get_power_domain_tree_desc(void)
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{
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{
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return sgi_pd_tree_desc;
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if (sgi_plat_info.platform_id == SGI_CLARK_SID_VER_PART_NUM &&
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sgi_plat_info.config_id == SGI_CLARK_HELIOS_CONFIG_ID)
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return sgi_clark_helios_pd_tree_desc;
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else
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return sgi_pd_tree_desc;
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}
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}
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/*******************************************************************************
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/*******************************************************************************
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