Tegra194: rename secure scratch register macros
This patch renames all the secure scratch registers to reflect their usage. This is a list of all the macros being renamed: - SECURE_SCRATCH_RSV44_* -> SCRATCH_BOOT_PARAMS_ADDR_* - SECURE_SCRATCH_RSV97 -> SCRATCH_SECURE_BOOTP_FCFG - SECURE_SCRATCH_RSV99_* -> SCRATCH_SMMU_TABLE_ADDR_* - SECURE_SCRATCH_RSV109_* -> SCRATCH_RESET_VECTOR_* Change-Id: I838ece3da39bc4be8f349782e99bac777755fa39 Signed-off-by: Steven Kao <skao@nvidia.com>
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@ -156,16 +156,21 @@
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* Tegra scratch registers constants
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******************************************************************************/
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#define TEGRA_SCRATCH_BASE U(0x0C390000)
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#define SECURE_SCRATCH_RSV1_LO U(0x06C)
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#define SECURE_SCRATCH_RSV1_HI U(0x070)
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#define SECURE_SCRATCH_RSV6 U(0x094)
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#define SECURE_SCRATCH_RSV11_LO U(0x0BC)
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#define SECURE_SCRATCH_RSV11_HI U(0x0C0)
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#define SECURE_SCRATCH_RSV53_LO U(0x20C)
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#define SECURE_SCRATCH_RSV53_HI U(0x210)
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#define SECURE_SCRATCH_RSV54_HI U(0x218)
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#define SECURE_SCRATCH_RSV55_LO U(0x21C)
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#define SECURE_SCRATCH_RSV55_HI U(0x220)
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#define SECURE_SCRATCH_RSV44_LO U(0x1C4)
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#define SECURE_SCRATCH_RSV44_HI U(0x1C8)
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#define SECURE_SCRATCH_RSV97 U(0x36C)
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#define SECURE_SCRATCH_RSV99_LO U(0x37C)
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#define SECURE_SCRATCH_RSV99_HI U(0x380)
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#define SECURE_SCRATCH_RSV109_LO U(0x3CC)
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#define SECURE_SCRATCH_RSV109_HI U(0x3D0)
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#define SCRATCH_BL31_PARAMS_ADDR SECURE_SCRATCH_RSV44_LO
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#define SCRATCH_BL31_PLAT_PARAMS_ADDR SECURE_SCRATCH_RSV44_HI
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#define SCRATCH_SECURE_BOOTP_FCFG SECURE_SCRATCH_RSV97
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#define SCRATCH_SMMU_TABLE_ADDR_LO SECURE_SCRATCH_RSV99_LO
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#define SCRATCH_SMMU_TABLE_ADDR_HI SECURE_SCRATCH_RSV99_HI
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#define SCRATCH_RESET_VECTOR_LO SECURE_SCRATCH_RSV109_LO
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#define SCRATCH_RESET_VECTOR_HI SECURE_SCRATCH_RSV109_HI
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/*******************************************************************************
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* Tegra Memory Mapped Control Register Access Bus constants
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@ -144,7 +144,7 @@ int32_t tegra_soc_pwr_domain_suspend(const psci_power_state_t *target_state)
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/* save 'Secure Boot' Processor Feature Config Register */
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val = mmio_read_32(TEGRA_MISC_BASE + MISCREG_PFCFG);
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mmio_write_32(TEGRA_SCRATCH_BASE + SECURE_SCRATCH_RSV6, val);
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mmio_write_32(TEGRA_SCRATCH_BASE + SCRATCH_SECURE_BOOTP_FCFG, val);
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#if ENABLE_SYSTEM_SUSPEND_CTX_SAVE_TZDRAM
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/* save SMMU context */
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@ -55,8 +55,8 @@ void plat_secondary_setup(void)
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mmio_write_32(TEGRA_MISC_BASE + MISCREG_AA64_RST_HIGH, addr_high);
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/* save reset vector to be used during SYSTEM_SUSPEND exit */
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mmio_write_32(TEGRA_SCRATCH_BASE + SECURE_SCRATCH_RSV1_LO,
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mmio_write_32(TEGRA_SCRATCH_BASE + SCRATCH_RESET_VECTOR_LO,
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addr_low);
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mmio_write_32(TEGRA_SCRATCH_BASE + SECURE_SCRATCH_RSV1_HI,
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mmio_write_32(TEGRA_SCRATCH_BASE + SCRATCH_RESET_VECTOR_HI,
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addr_high);
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}
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@ -269,7 +269,7 @@ struct tegra_bl31_params *plat_get_bl31_params(void)
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{
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uint32_t val;
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val = mmio_read_32(TEGRA_SCRATCH_BASE + SECURE_SCRATCH_RSV53_LO);
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val = mmio_read_32(TEGRA_SCRATCH_BASE + SCRATCH_BL31_PARAMS_ADDR);
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return (struct tegra_bl31_params *)(uintptr_t)val;
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}
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@ -281,7 +281,7 @@ plat_params_from_bl2_t *plat_get_bl31_plat_params(void)
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{
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uint32_t val;
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val = mmio_read_32(TEGRA_SCRATCH_BASE + SECURE_SCRATCH_RSV53_HI);
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val = mmio_read_32(TEGRA_SCRATCH_BASE + SCRATCH_BL31_PLAT_PARAMS_ADDR);
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return (plat_params_from_bl2_t *)(uintptr_t)val;
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}
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