arm_fpga: Add support for unknown MPIDs
This patch allows the system to fallback to a default CPU library in case the MPID does not match with any of the supported ones. This feature can be enabled by setting SUPPORT_UNKNOWN_MPID build option to 1 (enabled by default only on arm_fpga platform). This feature can be very dangerous on a production image and therefore it MUST be disabled for Release images. Signed-off-by: Javier Almansa Sobrino <javier.almansasobrino@arm.com> Change-Id: I0df7ef2b012d7d60a4fd5de44dea1fbbb46881ba
This commit is contained in:
Javier Almansa Sobrino
parent
73740d98d9
commit
1994e56221
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@ -7,6 +7,12 @@
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################################################################################
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# Include Makefile for the SPM-MM implementation
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################################################################################
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ifeq (${SUPPORT_UNKNOWN_MPID},1)
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ifeq (${DEBUG},0)
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$(warning WARNING: SUPPORT_UNKNOWN_MPID enabled)
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endif
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endif
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ifeq (${SPM_MM},1)
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ifeq (${EL3_EXCEPTION_HANDLING},0)
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$(error EL3_EXCEPTION_HANDLING must be 1 for SPM-MM support)
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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@ -41,6 +41,15 @@ static int32_t (*bl32_init)(void);
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******************************************************************************/
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static uint32_t next_image_type = NON_SECURE;
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#ifdef SUPPORT_UNKNOWN_MPID
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/*
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* Flag to know whether an unsupported MPID has been detected. To avoid having it
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* landing on the .bss section, it is initialized to a non-zero value, this way
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* we avoid potential WAW hazards during system bring up.
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* */
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volatile uint32_t unsupported_mpid_flag = 1;
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#endif
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/*
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* Implement the ARM Standard Service function to get arguments for a
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* particular service.
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@ -98,6 +107,12 @@ void bl31_main(void)
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NOTICE("BL31: %s\n", version_string);
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NOTICE("BL31: %s\n", build_message);
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#ifdef SUPPORT_UNKNOWN_MPID
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if (unsupported_mpid_flag == 0) {
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NOTICE("Unsupported MPID detected!\n");
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}
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#endif
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/* Perform platform setup in BL31 */
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bl31_platform_setup();
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@ -0,0 +1,18 @@
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/*
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* Copyright (c) 2020, Arm Limited. All rights reserverd.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef AARCH64_GENERIC_H
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#define AARCH64_GENERIC_H
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#include <lib/utils_def.h>
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/*
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* 0x0 value on the MIDR implementer value is reserved for software use,
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* so use an MIDR value of 0 for a default CPU library.
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*/
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#define AARCH64_GENERIC_MIDR U(0)
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#endif /* AARCH64_GENERIC_H */
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2014-2019, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2014-2020, Arm Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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@ -140,6 +140,13 @@ endfunc do_cpu_reg_dump
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* midr of the core. It reads the MIDR_EL1 and finds the matching
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* entry in cpu_ops entries. Only the implementation and part number
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* are used to match the entries.
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*
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* If cpu_ops for the MIDR_EL1 cannot be found and
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* SUPPORT_UNKNOWN_MPID is enabled, it will try to look for a
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* default cpu_ops with an MIDR value of 0.
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* (Implementation number 0x0 should be reseverd for software use
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* and therefore no clashes should happen with that default value).
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*
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* Return :
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* x0 - The matching cpu_ops pointer on Success
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* x0 - 0 on failure.
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@ -147,23 +154,26 @@ endfunc do_cpu_reg_dump
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*/
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.globl get_cpu_ops_ptr
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func get_cpu_ops_ptr
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/* Get the cpu_ops start and end locations */
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adr x4, (__CPU_OPS_START__ + CPU_MIDR)
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adr x5, (__CPU_OPS_END__ + CPU_MIDR)
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/* Initialize the return parameter */
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mov x0, #0
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/* Read the MIDR_EL1 */
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mrs x2, midr_el1
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mov_imm x3, CPU_IMPL_PN_MASK
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/* Retain only the implementation and part number using mask */
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and w2, w2, w3
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/* Get the cpu_ops end location */
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adr x5, (__CPU_OPS_END__ + CPU_MIDR)
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/* Initialize the return parameter */
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mov x0, #0
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1:
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/* Get the cpu_ops start location */
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adr x4, (__CPU_OPS_START__ + CPU_MIDR)
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2:
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/* Check if we have reached end of list */
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cmp x4, x5
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b.eq error_exit
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b.eq search_def_ptr
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/* load the midr from the cpu_ops */
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ldr x1, [x4], #CPU_OPS_SIZE
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@ -171,7 +181,7 @@ func get_cpu_ops_ptr
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/* Check if midr matches to midr of this core */
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cmp w1, w2
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b.ne 1b
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b.ne 2b
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/* Subtract the increment and offset to get the cpu-ops pointer */
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sub x0, x4, #(CPU_OPS_SIZE + CPU_MIDR)
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@ -179,7 +189,27 @@ func get_cpu_ops_ptr
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cmp x0, #0
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ASM_ASSERT(ne)
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#endif
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#ifdef SUPPORT_UNKNOWN_MPID
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cbnz x2, exit_mpid_found
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/* Mark the unsupported MPID flag */
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adrp x1, unsupported_mpid_flag
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add x1, x1, :lo12:unsupported_mpid_flag
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str w2, [x1]
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exit_mpid_found:
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#endif
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ret
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/*
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* Search again for a default pointer (MIDR = 0x0)
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* or return error if already searched.
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*/
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search_def_ptr:
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#ifdef SUPPORT_UNKNOWN_MPID
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cbz x2, error_exit
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mov x2, #0
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b 1b
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error_exit:
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#endif
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ret
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endfunc get_cpu_ops_ptr
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@ -0,0 +1,89 @@
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/*
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* Copyright (c) 2020, Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <asm_macros.S>
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#include <common/bl_common.h>
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#include <generic.h>
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#include <cpu_macros.S>
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#include <plat_macros.S>
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/* ---------------------------------------------
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* Disable L1 data cache and unified L2 cache
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* ---------------------------------------------
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*/
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func generic_disable_dcache
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mrs x1, sctlr_el3
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bic x1, x1, #SCTLR_C_BIT
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msr sctlr_el3, x1
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isb
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ret
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endfunc generic_disable_dcache
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func generic_core_pwr_dwn
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mov x18, x30
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/* ---------------------------------------------
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* Turn off caches.
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* ---------------------------------------------
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*/
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bl generic_disable_dcache
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/* ---------------------------------------------
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* Flush L1 caches.
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* ---------------------------------------------
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*/
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mov x0, #DCCISW
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bl dcsw_op_level1
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ret x18
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endfunc generic_core_pwr_dwn
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func generic_cluster_pwr_dwn
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mov x18, x30
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/* ---------------------------------------------
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* Turn off caches.
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* ---------------------------------------------
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*/
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bl generic_disable_dcache
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/* ---------------------------------------------
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* Flush L1 caches.
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* ---------------------------------------------
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*/
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mov x0, #DCCISW
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bl dcsw_op_level1
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/* ---------------------------------------------
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* Disable the optional ACP.
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* ---------------------------------------------
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*/
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bl plat_disable_acp
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/* ---------------------------------------------
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* Flush L2 caches.
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* ---------------------------------------------
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*/
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mov x0, #DCCISW
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bl dcsw_op_level2
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ret x18
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endfunc generic_cluster_pwr_dwn
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/* ---------------------------------------------
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* Unimplemented functions.
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* ---------------------------------------------
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*/
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.equ generic_errata_report, 0
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.equ generic_cpu_reg_dump, 0
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.equ generic_reset_func, 0
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declare_cpu_ops generic, AARCH64_GENERIC_MIDR, \
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generic_reset_func, \
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generic_core_pwr_dwn, \
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generic_cluster_pwr_dwn
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@ -1,5 +1,5 @@
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#
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# Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
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# Copyright (c) 2020, Arm Limited. All rights reserved.
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#
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# SPDX-License-Identifier: BSD-3-Clause
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#
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@ -40,6 +40,8 @@ HW_ASSISTED_COHERENCY := 1
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PL011_GENERIC_UART := 1
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SUPPORT_UNKNOWN_MPID ?= 1
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FPGA_CPU_LIBS := lib/cpus/${ARCH}/aem_generic.S
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# select a different set of CPU files, depending on whether we compile for
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@ -71,6 +73,12 @@ else
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lib/cpus/aarch64/cortex_a75.S
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endif
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ifeq (${SUPPORT_UNKNOWN_MPID}, 1)
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# Add support for unknown/invalid MPIDs (aarch64 only)
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$(eval $(call add_define,SUPPORT_UNKNOWN_MPID))
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FPGA_CPU_LIBS += lib/cpus/aarch64/generic.S
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endif
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# Allow detection of GIC-600
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GICV3_SUPPORT_GIC600 := 1
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