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arm_fpga: Read GICD and GICR base addresses from DT 

Since we use a DTB with all platform information to pass this on to a
kernel loaded as BL33, we can as well make use of it for our own
purposes.

Every DT would contain a node for the GIC(v3) interrupt controller, so
we can read the base address for the distributor and redistributors from
there.

This avoids hard coding this information in the code and allows for a more
flexible binary.

Change-Id: Ic530e223a21a45bc30a07a21048116d5af69e972
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
This commit is contained in:
Andre Przywara 2020-01-24 15:46:05 +00:00
parent 670c66af06
commit 1a0f9366d8
2 changed files with 29 additions and 6 deletions
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32
plat/arm/board/arm_fpga/fpga_gicv3.c
View File

@ -4,9 +4,13 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <common/debug.h>
#include <common/fdt_wrappers.h>
#include <drivers/arm/gicv3.h>
#include <drivers/arm/gic_common.h>
#include <libfdt.h>
#include <platform_def.h>
#include <plat/common/platform.h>
#include <platform_def.h>
@ -22,9 +26,7 @@ static unsigned int fpga_mpidr_to_core_pos(unsigned long mpidr)
return (unsigned int)plat_core_pos_by_mpidr(mpidr);
}
static const gicv3_driver_data_t fpga_gicv3_driver_data = {
.gicd_base = GICD_BASE,
.gicr_base = GICR_BASE,
static gicv3_driver_data_t fpga_gicv3_driver_data = {
.interrupt_props = fpga_interrupt_props,
.interrupt_props_num = ARRAY_SIZE(fpga_interrupt_props),
.rdistif_num = PLATFORM_CORE_COUNT,
@ -34,6 +36,30 @@ static const gicv3_driver_data_t fpga_gicv3_driver_data = {
void plat_fpga_gic_init(void)
{
const void *fdt = (void *)(uintptr_t)FPGA_PRELOADED_DTB_BASE;
int node, ret;
node = fdt_node_offset_by_compatible(fdt, 0, "arm,gic-v3");
if (node < 0) {
WARN("No \"arm,gic-v3\" compatible node found in DT, no GIC support.\n");
return;
}
/* TODO: Assuming only empty "ranges;" properties up the bus path. */
ret = fdt_get_reg_props_by_index(fdt, node, 0,
&fpga_gicv3_driver_data.gicd_base, NULL);
if (ret < 0) {
WARN("Could not read GIC distributor address from DT.\n");
return;
}
ret = fdt_get_reg_props_by_index(fdt, node, 1,
&fpga_gicv3_driver_data.gicr_base, NULL);
if (ret < 0) {
WARN("Could not read GIC redistributor address from DT.\n");
return;
}
gicv3_driver_init(&fpga_gicv3_driver_data);
gicv3_distif_init();
gicv3_rdistif_init(plat_my_core_pos());

3
plat/arm/board/arm_fpga/include/platform_def.h
View File

@ -35,9 +35,6 @@
#define BL31_LIMIT UL(0x01000000)
#endif
#define GICD_BASE 0x30000000
#define GICR_BASE 0x30040000
#define PLAT_SDEI_NORMAL_PRI 0x70
#define ARM_IRQ_SEC_PHY_TIMER 29