errata: workaround for Cortex A78 errata 1821534
Cortex A78 erratum 1821534 is a Cat B erratum present in r0p0 and r1p0 of the A78 processor core, it is fixed in r1p1. SDEN can be found here: https://documentation-service.arm.com/static/603e3733492bde1625aa8780 Signed-off-by: John Powell <john.powell@arm.com> Change-Id: I71057c4b9625cd9edc1a06946b453cf16ae5ea2c
This commit is contained in:
johpow01
bipin.ravi
parent
64b8db7e80
commit
1a691455d9
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@ -275,6 +275,9 @@ For Cortex-A78, the following errata build flags are defined :
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CPU. This needs to be enabled for revisions r1p0 and r1p1, r0p0 has the same
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issue but there is no workaround for that revision.
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- ``ERRATA_A78_1821534``: This applies errata 1821534 workaround to Cortex-A78
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CPU. This needs to be enabled for revisions r0p0 and r1p0.
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For Neoverse N1, the following errata build flags are defined :
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- ``ERRATA_N1_1073348``: This applies errata 1073348 workaround to Neoverse-N1
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@ -30,6 +30,7 @@
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#define CORTEX_A78_ACTLR2_EL1 S3_0_C15_C1_1
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#define CORTEX_A78_ACTLR2_EL1_BIT_1 (ULL(1) << 1)
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#define CORTEX_A78_ACTLR2_EL1_BIT_2 (ULL(1) << 2)
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/*******************************************************************************
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* CPU Activity Monitor Unit register specific definitions.
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@ -44,13 +44,13 @@ func check_errata_1688305
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b cpu_rev_var_ls
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endfunc check_errata_1688305
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/* --------------------------------------------------
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* Errata Workaround for Cortex A78 Errata #1941498.
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* This applies to revisions r0p0, r1p0, and r1p1.
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* x0: variant[4:7] and revision[0:3] of current cpu.
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* Shall clobber: x0-x17
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* --------------------------------------------------
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*/
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/* --------------------------------------------------
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* Errata Workaround for Cortex A78 Errata #1941498.
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* This applies to revisions r0p0, r1p0, and r1p1.
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* x0: variant[4:7] and revision[0:3] of current cpu.
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* Shall clobber: x0-x17
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* --------------------------------------------------
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*/
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func errata_a78_1941498_wa
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/* Compare x0 against revision <= r1p1 */
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mov x17, x30
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@ -72,16 +72,16 @@ func check_errata_1941498
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b cpu_rev_var_ls
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endfunc check_errata_1941498
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/* --------------------------------------------------
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* Errata Workaround for A78 Erratum 1951500.
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* This applies to revisions r1p0 and r1p1 of A78.
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* The issue also exists in r0p0 but there is no fix
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* in that revision.
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* Inputs:
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* x0: variant[4:7] and revision[0:3] of current cpu.
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* Shall clobber: x0-x17
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* --------------------------------------------------
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*/
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/* --------------------------------------------------
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* Errata Workaround for A78 Erratum 1951500.
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* This applies to revisions r1p0 and r1p1 of A78.
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* The issue also exists in r0p0 but there is no fix
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* in that revision.
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* Inputs:
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* x0: variant[4:7] and revision[0:3] of current cpu.
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* Shall clobber: x0-x17
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* --------------------------------------------------
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*/
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func errata_a78_1951500_wa
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/* Compare x0 against revisions r1p0 - r1p1 */
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mov x17, x30
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@ -126,6 +126,34 @@ func check_errata_1951500
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b cpu_rev_var_range
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endfunc check_errata_1951500
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/* --------------------------------------------------
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* Errata Workaround for Cortex A78 Errata #1821534.
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* This applies to revisions r0p0 and r1p0.
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* x0: variant[4:7] and revision[0:3] of current cpu.
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* Shall clobber: x0-x17
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* --------------------------------------------------
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*/
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func errata_a78_1821534_wa
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/* Check revision. */
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mov x17, x30
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bl check_errata_1821534
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cbz x0, 1f
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/* Set bit 2 in ACTLR2_EL1 */
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mrs x1, CORTEX_A78_ACTLR2_EL1
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orr x1, x1, #CORTEX_A78_ACTLR2_EL1_BIT_2
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msr CORTEX_A78_ACTLR2_EL1, x1
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isb
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1:
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ret x17
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endfunc errata_a78_1821534_wa
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func check_errata_1821534
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/* Applies to r0p0 and r1p0 */
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mov x1, #0x10
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b cpu_rev_var_ls
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endfunc check_errata_1821534
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/* -------------------------------------------------
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* The CPU Ops reset function for Cortex-A78
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* -------------------------------------------------
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@ -150,6 +178,11 @@ func cortex_a78_reset_func
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bl errata_a78_1951500_wa
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#endif
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#if ERRATA_A78_1821534
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mov x0, x18
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bl errata_a78_1821534_wa
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#endif
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#if ENABLE_AMU
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/* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */
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mrs x0, actlr_el3
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@ -207,6 +240,7 @@ func cortex_a78_errata_report
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report_errata ERRATA_A78_1688305, cortex_a78, 1688305
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report_errata ERRATA_A78_1941498, cortex_a78, 1941498
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report_errata ERRATA_A78_1951500, cortex_a78, 1951500
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report_errata ERRATA_A78_1821534, cortex_a78, 1821534
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ldp x8, x30, [sp], #16
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ret
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@ -307,6 +307,10 @@ ERRATA_A78_1941498 ?=0
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# well but there is no workaround for that revision.
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ERRATA_A78_1951500 ?=0
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# Flag to apply erratum 1821534 workaround during reset. This erratum applies
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# to revisions r0p0 and r1p0 of the A78 cpu.
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ERRATA_A78_1821534 ?=0
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# Flag to apply T32 CLREX workaround during reset. This erratum applies
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# only to r0p0 and r1p0 of the Neoverse N1 cpu.
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ERRATA_N1_1043202 ?=0
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@ -605,6 +609,10 @@ $(eval $(call add_define,ERRATA_A78_1941498))
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$(eval $(call assert_boolean,ERRATA_A78_1951500))
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$(eval $(call add_define,ERRATA_A78_1951500))
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# Process ERRATA_A78_1821534 flag
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$(eval $(call assert_boolean,ERRATA_A78_1821534))
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$(eval $(call add_define,ERRATA_A78_1821534))
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# Process ERRATA_N1_1043202 flag
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$(eval $(call assert_boolean,ERRATA_N1_1043202))
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$(eval $(call add_define,ERRATA_N1_1043202))
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