plat: svc: ap807: add SVC configuration for AP807
- add svc configuration according to values burnt to the chip efuse Change-Id: Icf5d7cc41bc09ac2244d0a126106e681afebb064 Signed-off-by: Christine Gharzuzi <chrisg@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
This commit is contained in:
Christine Gharzuzi
Konstantin Porotchkin
parent
6384f0acf0
commit
1ab4df76bf
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@ -29,6 +29,7 @@ enum cpu_clock_freq_mode {
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CPU_1800_DDR_1050_RCLK_1050 = 0x7,
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CPU_1600_DDR_900_RCLK_900 = 0x0B,
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CPU_1600_DDR_1050_RCLK_1050 = 0x0D,
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CPU_1600_DDR_1200_RCLK_1200 = 0x0D,
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CPU_1600_DDR_900_RCLK_900_2 = 0x0E,
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CPU_1000_DDR_650_RCLK_650 = 0x13,
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CPU_1300_DDR_800_RCLK_800 = 0x14,
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@ -20,6 +20,7 @@
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#define MVEBU_DEVICE_REV_MASK (0xf << MVEBU_DEVICE_REV_OFFSET)
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#define MVEBU_70X0_DEV_ID (0x7040)
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#define MVEBU_70X0_CP115_DEV_ID (0x7045)
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#define MVEBU_3900_DEV_ID (0x6025)
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#define MVEBU_80X0_DEV_ID (0x8040)
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#define MVEBU_80X0_CP115_DEV_ID (0x8045)
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#define MVEBU_CP110_SA_DEV_ID (0x110)
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@ -43,11 +43,22 @@
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#define AVS_EN_CTRL_REG (MVEBU_AP_GEN_MGMT_BASE + 0x130)
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#define AVS_ENABLE_OFFSET (0)
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#define AVS_SOFT_RESET_OFFSET (2)
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#define AVS_LOW_VDD_LIMIT_OFFSET (4)
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#define AVS_HIGH_VDD_LIMIT_OFFSET (12)
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#define AVS_TARGET_DELTA_OFFSET (21)
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#define AVS_VDD_LOW_LIMIT_MASK (0xFF << AVS_LOW_VDD_LIMIT_OFFSET)
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#define AVS_VDD_HIGH_LIMIT_MASK (0xFF << AVS_HIGH_VDD_LIMIT_OFFSET)
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#ifndef MVEBU_SOC_AP807
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/* AP806 SVC bits */
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#define AVS_LOW_VDD_LIMIT_OFFSET (4)
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#define AVS_HIGH_VDD_LIMIT_OFFSET (12)
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#define AVS_VDD_LOW_LIMIT_MASK (0xFF << AVS_LOW_VDD_LIMIT_OFFSET)
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#define AVS_VDD_HIGH_LIMIT_MASK (0xFF << AVS_HIGH_VDD_LIMIT_OFFSET)
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#else
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/* AP807 SVC bits */
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#define AVS_LOW_VDD_LIMIT_OFFSET (3)
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#define AVS_HIGH_VDD_LIMIT_OFFSET (13)
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#define AVS_VDD_LOW_LIMIT_MASK (0x3FF << AVS_LOW_VDD_LIMIT_OFFSET)
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#define AVS_VDD_HIGH_LIMIT_MASK (0x3FF << AVS_HIGH_VDD_LIMIT_OFFSET)
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#endif
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/* VDD limit is 0.9V for A70x0 @ CPU frequency < 1600MHz */
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#define AVS_A7K_LOW_CLK_VALUE ((0x80 << AVS_TARGET_DELTA_OFFSET) | \
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(0x1A << AVS_HIGH_VDD_LIMIT_OFFSET) | \
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@ -84,11 +95,6 @@
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#define AP807_CPU_ARO_SEL_PLL_MASK (0x1 << AP807_CPU_ARO_SEL_PLL_OFFSET)
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/*
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* - AVS work points in the LD0 eFuse:
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* SVC1 work point: LD0[88:81]
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* SVC2 work point: LD0[96:89]
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* SVC3 work point: LD0[104:97]
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* SVC4 work point: LD0[112:105]
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* - Identification information in the LD-0 eFuse:
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* DRO: LD0[74:65] - Not used by the SW
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* Revision: LD0[78:75] - Not used by the SW
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@ -114,11 +120,30 @@
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#define EFUSE_AP_LD0_SWREV_OFFS 50 /* LD0[115:113] */
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#define EFUSE_AP_LD0_SWREV_MASK 0x7
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#define EFUSE_AP_LD0_SVC1_OFFS 18 /* LD0[88:81] */
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#define EFUSE_AP_LD0_SVC2_OFFS 26 /* LD0[96:89] */
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#define EFUSE_AP_LD0_SVC3_OFFS 34 /* LD0[104:97] */
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#ifndef MVEBU_SOC_AP807
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/* AP806 AVS work points in the LD0 eFuse
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* SVC1 work point: LD0[88:81]
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* SVC2 work point: LD0[96:89]
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* SVC3 work point: LD0[104:97]
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* SVC4 work point: LD0[112:105]
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*/
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#define EFUSE_AP_LD0_SVC1_OFFS 18 /* LD0[88:81] */
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#define EFUSE_AP_LD0_SVC2_OFFS 26 /* LD0[96:89] */
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#define EFUSE_AP_LD0_SVC3_OFFS 34 /* LD0[104:97] */
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#define EFUSE_AP_LD0_WP_MASK 0xFF
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#else
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/* AP807 AVS work points in the LD0 eFuse
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* SVC1 work point: LD0[91:81]
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* SVC2 work point: LD0[102:92]
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* SVC3 work point: LD0[113:103]
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*/
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#define EFUSE_AP_LD0_SVC1_OFFS 17 /* LD0[91:81] */
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#define EFUSE_AP_LD0_SVC2_OFFS 28 /* LD0[102:92] */
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#define EFUSE_AP_LD0_SVC3_OFFS 39 /* LD0[113:103] */
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#define EFUSE_AP_LD0_WP_MASK 0x3FF
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#endif
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#define EFUSE_AP_LD0_SVC4_OFFS 42 /* LD0[112:105] */
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#define EFUSE_AP_LD0_WP_MASK 0xFF
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#define EFUSE_AP_LD0_CLUSTER_DOWN_OFFS 4
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@ -233,16 +258,8 @@ static void ble_plat_svc_config(void)
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uint32_t reg_val, avs_workpoint, freq_pidi_mode;
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uint64_t efuse;
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uint32_t device_id, single_cluster;
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uint8_t svc[4], perr[4], i, sw_ver;
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/* Due to a bug in A3900 device_id skip SVC config
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* TODO: add SVC config once it is decided for a3900
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*/
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if (ble_get_ap_type() == CHIP_ID_AP807) {
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NOTICE("SVC: SVC is not supported on AP807\n");
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ble_plat_avs_config();
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return;
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}
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uint16_t svc[4], perr[4], i, sw_ver;
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unsigned int ap_type;
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/* Set access to LD0 */
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reg_val = mmio_read_32(MVEBU_AP_EFUSE_SRV_CTRL_REG);
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@ -276,9 +293,19 @@ static void ble_plat_svc_config(void)
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svc[0] = (efuse >> EFUSE_AP_LD0_SVC1_OFFS) & EFUSE_AP_LD0_WP_MASK;
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svc[1] = (efuse >> EFUSE_AP_LD0_SVC2_OFFS) & EFUSE_AP_LD0_WP_MASK;
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svc[2] = (efuse >> EFUSE_AP_LD0_SVC3_OFFS) & EFUSE_AP_LD0_WP_MASK;
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svc[3] = (efuse >> EFUSE_AP_LD0_SVC4_OFFS) & EFUSE_AP_LD0_WP_MASK;
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INFO("SVC: Efuse WP: [0]=0x%x, [1]=0x%x, [2]=0x%x, [3]=0x%x\n",
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svc[0], svc[1], svc[2], svc[3]);
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/* Fetch AP type to distinguish between AP806 and AP807 */
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ap_type = ble_get_ap_type();
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if (ap_type != CHIP_ID_AP807) {
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svc[3] = (efuse >> EFUSE_AP_LD0_SVC4_OFFS)
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& EFUSE_AP_LD0_WP_MASK;
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INFO("SVC: Efuse WP: [0]=0x%x, [1]=0x%x, [2]=0x%x, [3]=0x%x\n",
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svc[0], svc[1], svc[2], svc[3]);
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} else {
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INFO("SVC: Efuse WP: [0]=0x%x, [1]=0x%x, [2]=0x%x\n",
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svc[0], svc[1], svc[2]);
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}
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/* Validate parity of SVC workpoint values */
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for (i = 0; i < 4; i++) {
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@ -385,6 +412,26 @@ static void ble_plat_svc_config(void)
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avs_workpoint = 0;
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break;
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}
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} else if (device_id == MVEBU_3900_DEV_ID) {
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NOTICE("SVC: DEV ID: %s, FREQ Mode: 0x%x\n",
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"3900", freq_pidi_mode);
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switch (freq_pidi_mode) {
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case CPU_1600_DDR_1200_RCLK_1200:
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if (perr[0])
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goto perror;
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avs_workpoint = svc[0];
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break;
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case CPU_1300_DDR_800_RCLK_800:
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if (perr[1])
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goto perror;
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avs_workpoint = svc[1];
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break;
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default:
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if (perr[0])
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goto perror;
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avs_workpoint = svc[0];
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break;
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}
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} else {
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ERROR("SVC: Unsupported Device ID 0x%x\n", device_id);
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return;
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@ -397,7 +444,8 @@ static void ble_plat_svc_config(void)
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}
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/* Remove parity bit */
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avs_workpoint &= 0x7F;
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if (ap_type != CHIP_ID_AP807)
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avs_workpoint &= 0x7F;
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reg_val = mmio_read_32(AVS_EN_CTRL_REG);
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NOTICE("SVC: AVS work point changed from 0x%x to 0x%x\n",
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