From 1bdbdc3b3f3068797a1539eacff727592762d5b9 Mon Sep 17 00:00:00 2001 From: Jeenu Viswambharan Date: Wed, 19 Jul 2017 17:27:49 +0100 Subject: [PATCH] Add Linux DTS for FVP with threaded CPUs In contrast with the non-multi-threading DTS, this enumerates MPIDR values shifted by one affinity level to the left. The newly added DTS reflects CPUs with a single thread in them. Since both DTS files are the same apart from MPIDR contents, the common bits have been moved to a separate file that's then included from the top-level DTS files. The multi-threading version only updates the MPIDR contents. Change-Id: Id225cd93574f764171df8962ac76f42fcb6bba4b Signed-off-by: Jeenu Viswambharan --- fdts/fvp-base-gicv3-psci-1t.dtb | Bin 0 -> 9314 bytes fdts/fvp-base-gicv3-psci-1t.dts | 41 ++++ fdts/fvp-base-gicv3-psci-common.dtsi | 268 +++++++++++++++++++++++++++ fdts/fvp-base-gicv3-psci.dts | 263 +------------------------- 4 files changed, 310 insertions(+), 262 deletions(-) create mode 100644 fdts/fvp-base-gicv3-psci-1t.dtb create mode 100644 fdts/fvp-base-gicv3-psci-1t.dts create mode 100644 fdts/fvp-base-gicv3-psci-common.dtsi diff --git a/fdts/fvp-base-gicv3-psci-1t.dtb b/fdts/fvp-base-gicv3-psci-1t.dtb new file mode 100644 index 0000000000000000000000000000000000000000..23d360fc2755ccb504afa4264a4105ea0b5a64bc GIT binary patch literal 9314 zcmb_i&5s;M6|deUOAG`j7z84qSXqQjw4I%q^(GsH$;4|rSn-!EV?{{OsHdlAw{d@^ zyJx%`4lyF)0@onK2?-E)F5wSIByL#TBbgf#AMyb>27bR+RXx?-*_GGpl6w2Sdaqvn z>eZ`P)irzfsZai?)HjAosqZOu@*jAg!t)HCr}3aHPEr3`Qg`@=#nZ0`{@U6_)E}el z!p&;Kcq~UXs0Nns?v(o`xG8xpiRp^4|>7jyN36|?YxRI za9ZvKNes(kjcr%)oLQ~X;cA-K+fg~pgL1SQ=i_24=&!AGOj(@-W!>+*LYAhaU$#B} z&~1Y~Z7)A`+u@$J-+$<~VbhlW@ro*pIRF%ne;JSXob`V9#g6z~n9hs6hM{`n>$j>j zbotST?YSu4YtO|Fsc!V=%`McG2VFl63QZ@Is*XxM zJCx;RWEk7;FH9f0AIKRbD6X7zBkzg0B`5wyzP4BXgpq3Q#&?ASx51MmiAn*FtKMFqSq3KTnpZD)sf9f7Ye{*=? zJNDs>m)4(kc;X}9_!;rpZ^xi_9Cc8UF>);8OZa`d!CGC9`ShOEY*UB0@}6_%hCZU6 zk2meOIL?6o93Iz?#AJEmY+-E2++i_FYNzd^Vx$chBWXR?@MAmf4~vmz#P(4!GOk^W zl1`>1oxy~Sdn5AA;BB|Se3 z!fkh-W*jU@B?uJTj+5% zjho|G$H!px=y$1$>xypZS!Wxa=6s<2;6n`(-5xLRr-lYN?aYNTl`Nc^*@XG^A3&qY3i|G3T?;q{uBTCEBl%C+wTP%NR-Z5|BG(_ zFYEq-4oPBWete#|NqqL}&3_F?*bs2K3ZWspY1vev?a`SE^ddZ0Z!f9#LnPx-#vhe$iErFkYCF@p|JVsJ8o^<|~w)qp<(4<7xHh zi?RyGv7xA`b>W8DdD0!bq3w7+f?@D@dO%y%6<*zn%>vX`tJxy1Vz)A;QJChaZ7c~FN6V(g0iU&SkQW?# zu2g7M>vEau+@1~t$qem9WBe;Q)8+*9rx+!cCpMcSsISyX`Ri4?RT*vdJF|2y_?mof z*Q>7;*@*4=ZS}0qm&^oGhnIKX(CA+xl79?7i3ciMp7B6l#t-vho%G!elX}hAs{%WY zzHce9^@UNAK{vnRU_NE zYo2=vrKV5uh4lf>FbgMIqc&L5lvvjH!P4D0(EqYCH2!B!<(Y%Uo|#DVTioK}9C2Te zMiio$aV(qy&3gKd#g3z^K4AK6_*X$cV|c`5Gfq2J%>BZNz0<6He=EgsU$Vm$n@zmI z_v;6amnZT0zGvLoG0wwuf|%a8eDV7E3!9hTXvd$#gy4Gl5pglP=Hud8I1;W0E_pd8 zuD`G?$qm{3^~orhkBgCW5H8H`!U^`hXSG6rww}h-Tp%9~7b9{$F3#{{z|~w%9}X8+ z@O)gH;m3fhx%fUDE=Ko!T!{6f;krG-ZwT_~$UfTZ5&6Hfeo%aI#m~n@!Gr$dTCh1n z;_LP(-`X#}B;WVD&K9{B+v$U_F+az$tlMx^FKL~XG>vn% zrft~5IgbeEkLLvlI3D&P{m6F&PLz`*sPocZ?~5%4(^4byMH5xc7)EP1-E-4IrFuX3 zwIlzT!=rlPH#3=>ExF2!Kja>UykJVh5TwYK@os&et>D^f9B<7zR$E&OAE1q#Me+*q zNlV%m?YC_CP!Oq>a~}Qzo@Ts>ecNNSb45UZa zQ;&8y8U1ZTWNHw;lNv(7@5?zX_U!`mnS3)`hc!o0qSi zJ3qK`^~%L7H_l(b^xEcmTG2Yln~UL%ip6;E^VH> zap8s%`t0l1HG#^Tn^!MiJJtQxtj#I3NjD)HY`%7Fu)eUfw$YIgBk1Z9-fYB?B<_>Txazs)MOT*dE1hOVMA4w8=2Z(RBa z-!tzumE!gzA1VB9FsLR~5oMar$789>GlkE?L6P5%O4gAs?i$4e(p!+2 z>&L3j3!SC;+r2UD11&CObR*=bC<}LeT((6!aqT;N8fQNGh(}f-iL=ShO0gYe_;px~ zqG=pPgL=1!6jB=O1#pT*0a*U*2jEI&(GHA9(^440~v+A8AQ?P^(9$kd8@WqQ}@;mD^#rEV97NP`^**%aTFn1Z56b`?WOO{!=x zN&^jfI2n(Dc(ymtsKatH(l{*hX`a+>J^GkeA0)Sf-O5MYh!gCUqfPZ?Jlbmi^NhLO zSQ$^U5Rjs`eVGt+1*Y0oJNT=1`KO3?WcVtH#`Pc#%B?t4WxTcBFc@T1T1mo~waj+4 gn}ve}|86sFC=zNaF2Rwlr^2kpG7E}I4U0nk9|oDzbpQYW literal 0 HcmV?d00001 diff --git a/fdts/fvp-base-gicv3-psci-1t.dts b/fdts/fvp-base-gicv3-psci-1t.dts new file mode 100644 index 000000000..36fbd4444 --- /dev/null +++ b/fdts/fvp-base-gicv3-psci-1t.dts @@ -0,0 +1,41 @@ +/* + * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/dts-v1/; + +/include/ "fvp-base-gicv3-psci-common.dtsi" + +&CPU0 { + reg = <0x0 0x0>; +}; + +&CPU1 { + reg = <0x0 0x100>; +}; + +&CPU2 { + reg = <0x0 0x200>; +}; + +&CPU3 { + reg = <0x0 0x300>; +}; + +&CPU4 { + reg = <0x0 0x10000>; +}; + +&CPU5 { + reg = <0x0 0x10100>; +}; + +&CPU6 { + reg = <0x0 0x10200>; +}; + +&CPU7 { + reg = <0x0 0x10300>; +}; diff --git a/fdts/fvp-base-gicv3-psci-common.dtsi b/fdts/fvp-base-gicv3-psci-common.dtsi new file mode 100644 index 000000000..2ef2df8dd --- /dev/null +++ b/fdts/fvp-base-gicv3-psci-common.dtsi @@ -0,0 +1,268 @@ +/* + * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/memreserve/ 0x80000000 0x00010000; + +/ { +}; + +/ { + model = "FVP Base"; + compatible = "arm,vfp-base", "arm,vexpress"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + chosen { }; + + aliases { + serial0 = &v2m_serial0; + serial1 = &v2m_serial1; + serial2 = &v2m_serial2; + serial3 = &v2m_serial3; + }; + + psci { + compatible = "arm,psci-1.0", "arm,psci-0.2", "arm,psci"; + method = "smc"; + cpu_suspend = <0xc4000001>; + cpu_off = <0x84000002>; + cpu_on = <0xc4000003>; + sys_poweroff = <0x84000008>; + sys_reset = <0x84000009>; + }; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + cpu-map { + cluster0 { + core0 { + cpu = <&CPU0>; + }; + core1 { + cpu = <&CPU1>; + }; + core2 { + cpu = <&CPU2>; + }; + core3 { + cpu = <&CPU3>; + }; + }; + + cluster1 { + core0 { + cpu = <&CPU4>; + }; + core1 { + cpu = <&CPU5>; + }; + core2 { + cpu = <&CPU6>; + }; + core3 { + cpu = <&CPU7>; + }; + }; + }; + + idle-states { + entry-method = "arm,psci"; + + CPU_SLEEP_0: cpu-sleep-0 { + compatible = "arm,idle-state"; + local-timer-stop; + arm,psci-suspend-param = <0x0010000>; + entry-latency-us = <40>; + exit-latency-us = <100>; + min-residency-us = <150>; + }; + + CLUSTER_SLEEP_0: cluster-sleep-0 { + compatible = "arm,idle-state"; + local-timer-stop; + arm,psci-suspend-param = <0x1010000>; + entry-latency-us = <500>; + exit-latency-us = <1000>; + min-residency-us = <2500>; + }; + }; + + CPU0:cpu@0 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x0>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + next-level-cache = <&L2_0>; + }; + + CPU1:cpu@1 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x1>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + next-level-cache = <&L2_0>; + }; + + CPU2:cpu@2 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x2>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + next-level-cache = <&L2_0>; + }; + + CPU3:cpu@3 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x3>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + next-level-cache = <&L2_0>; + }; + + CPU4:cpu@100 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x100>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + next-level-cache = <&L2_0>; + }; + + CPU5:cpu@101 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x101>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + next-level-cache = <&L2_0>; + }; + + CPU6:cpu@102 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x102>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + next-level-cache = <&L2_0>; + }; + + CPU7:cpu@103 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x103>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + next-level-cache = <&L2_0>; + }; + + L2_0: l2-cache0 { + compatible = "cache"; + }; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x00000000 0x80000000 0 0x7F000000>, + <0x00000008 0x80000000 0 0x80000000>; + }; + + gic: interrupt-controller@2f000000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <3>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + interrupt-controller; + reg = <0x0 0x2f000000 0 0x10000>, // GICD + <0x0 0x2f100000 0 0x200000>, // GICR + <0x0 0x2c000000 0 0x2000>, // GICC + <0x0 0x2c010000 0 0x2000>, // GICH + <0x0 0x2c02f000 0 0x2000>; // GICV + interrupts = <1 9 4>; + + its: its@2f020000 { + compatible = "arm,gic-v3-its"; + msi-controller; + reg = <0x0 0x2f020000 0x0 0x20000>; // GITS + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <1 13 0xff01>, + <1 14 0xff01>, + <1 11 0xff01>, + <1 10 0xff01>; + clock-frequency = <100000000>; + }; + + timer@2a810000 { + compatible = "arm,armv7-timer-mem"; + reg = <0x0 0x2a810000 0x0 0x10000>; + clock-frequency = <100000000>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + frame@2a830000 { + frame-number = <1>; + interrupts = <0 26 4>; + reg = <0x0 0x2a830000 0x0 0x10000>; + }; + }; + + pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = <0 60 4>, + <0 61 4>, + <0 62 4>, + <0 63 4>; + }; + + smb { + compatible = "simple-bus"; + + #address-cells = <2>; + #size-cells = <1>; + ranges = <0 0 0 0x08000000 0x04000000>, + <1 0 0 0x14000000 0x04000000>, + <2 0 0 0x18000000 0x04000000>, + <3 0 0 0x1c000000 0x04000000>, + <4 0 0 0x0c000000 0x04000000>, + <5 0 0 0x10000000 0x04000000>; + + /include/ "rtsm_ve-motherboard.dtsi" + }; + + panels { + panel@0 { + compatible = "panel"; + mode = "XVGA"; + refresh = <60>; + xres = <1024>; + yres = <768>; + pixclock = <15748>; + left_margin = <152>; + right_margin = <48>; + upper_margin = <23>; + lower_margin = <3>; + hsync_len = <104>; + vsync_len = <4>; + sync = <0>; + vmode = "FB_VMODE_NONINTERLACED"; + tim2 = "TIM2_BCD", "TIM2_IPC"; + cntl = "CNTL_LCDTFT", "CNTL_BGR", "CNTL_LCDVCOMP(1)"; + caps = "CLCD_CAP_5551", "CLCD_CAP_565", "CLCD_CAP_888"; + bpp = <16>; + }; + }; +}; diff --git a/fdts/fvp-base-gicv3-psci.dts b/fdts/fvp-base-gicv3-psci.dts index d81bfbb7b..3ea429ce9 100644 --- a/fdts/fvp-base-gicv3-psci.dts +++ b/fdts/fvp-base-gicv3-psci.dts @@ -6,265 +6,4 @@ /dts-v1/; -/memreserve/ 0x80000000 0x00010000; - -/ { -}; - -/ { - model = "FVP Base"; - compatible = "arm,vfp-base", "arm,vexpress"; - interrupt-parent = <&gic>; - #address-cells = <2>; - #size-cells = <2>; - - chosen { }; - - aliases { - serial0 = &v2m_serial0; - serial1 = &v2m_serial1; - serial2 = &v2m_serial2; - serial3 = &v2m_serial3; - }; - - psci { - compatible = "arm,psci-1.0", "arm,psci-0.2", "arm,psci"; - method = "smc"; - cpu_suspend = <0xc4000001>; - cpu_off = <0x84000002>; - cpu_on = <0xc4000003>; - sys_poweroff = <0x84000008>; - sys_reset = <0x84000009>; - }; - - cpus { - #address-cells = <2>; - #size-cells = <0>; - - cpu-map { - cluster0 { - core0 { - cpu = <&CPU0>; - }; - core1 { - cpu = <&CPU1>; - }; - core2 { - cpu = <&CPU2>; - }; - core3 { - cpu = <&CPU3>; - }; - }; - - cluster1 { - core0 { - cpu = <&CPU4>; - }; - core1 { - cpu = <&CPU5>; - }; - core2 { - cpu = <&CPU6>; - }; - core3 { - cpu = <&CPU7>; - }; - }; - }; - - idle-states { - entry-method = "arm,psci"; - - CPU_SLEEP_0: cpu-sleep-0 { - compatible = "arm,idle-state"; - local-timer-stop; - arm,psci-suspend-param = <0x0010000>; - entry-latency-us = <40>; - exit-latency-us = <100>; - min-residency-us = <150>; - }; - - CLUSTER_SLEEP_0: cluster-sleep-0 { - compatible = "arm,idle-state"; - local-timer-stop; - arm,psci-suspend-param = <0x1010000>; - entry-latency-us = <500>; - exit-latency-us = <1000>; - min-residency-us = <2500>; - }; - }; - - CPU0:cpu@0 { - device_type = "cpu"; - compatible = "arm,armv8"; - reg = <0x0 0x0>; - enable-method = "psci"; - cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; - next-level-cache = <&L2_0>; - }; - - CPU1:cpu@1 { - device_type = "cpu"; - compatible = "arm,armv8"; - reg = <0x0 0x1>; - enable-method = "psci"; - cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; - next-level-cache = <&L2_0>; - }; - - CPU2:cpu@2 { - device_type = "cpu"; - compatible = "arm,armv8"; - reg = <0x0 0x2>; - enable-method = "psci"; - cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; - next-level-cache = <&L2_0>; - }; - - CPU3:cpu@3 { - device_type = "cpu"; - compatible = "arm,armv8"; - reg = <0x0 0x3>; - enable-method = "psci"; - cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; - next-level-cache = <&L2_0>; - }; - - CPU4:cpu@100 { - device_type = "cpu"; - compatible = "arm,armv8"; - reg = <0x0 0x100>; - enable-method = "psci"; - cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; - next-level-cache = <&L2_0>; - }; - - CPU5:cpu@101 { - device_type = "cpu"; - compatible = "arm,armv8"; - reg = <0x0 0x101>; - enable-method = "psci"; - cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; - next-level-cache = <&L2_0>; - }; - - CPU6:cpu@102 { - device_type = "cpu"; - compatible = "arm,armv8"; - reg = <0x0 0x102>; - enable-method = "psci"; - cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; - next-level-cache = <&L2_0>; - }; - - CPU7:cpu@103 { - device_type = "cpu"; - compatible = "arm,armv8"; - reg = <0x0 0x103>; - enable-method = "psci"; - cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; - next-level-cache = <&L2_0>; - }; - - L2_0: l2-cache0 { - compatible = "cache"; - }; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x00000000 0x80000000 0 0x7F000000>, - <0x00000008 0x80000000 0 0x80000000>; - }; - - gic: interrupt-controller@2f000000 { - compatible = "arm,gic-v3"; - #interrupt-cells = <3>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - interrupt-controller; - reg = <0x0 0x2f000000 0 0x10000>, // GICD - <0x0 0x2f100000 0 0x200000>, // GICR - <0x0 0x2c000000 0 0x2000>, // GICC - <0x0 0x2c010000 0 0x2000>, // GICH - <0x0 0x2c02f000 0 0x2000>; // GICV - interrupts = <1 9 4>; - - its: its@2f020000 { - compatible = "arm,gic-v3-its"; - msi-controller; - reg = <0x0 0x2f020000 0x0 0x20000>; // GITS - }; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = <1 13 0xff01>, - <1 14 0xff01>, - <1 11 0xff01>, - <1 10 0xff01>; - clock-frequency = <100000000>; - }; - - timer@2a810000 { - compatible = "arm,armv7-timer-mem"; - reg = <0x0 0x2a810000 0x0 0x10000>; - clock-frequency = <100000000>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - frame@2a830000 { - frame-number = <1>; - interrupts = <0 26 4>; - reg = <0x0 0x2a830000 0x0 0x10000>; - }; - }; - - pmu { - compatible = "arm,armv8-pmuv3"; - interrupts = <0 60 4>, - <0 61 4>, - <0 62 4>, - <0 63 4>; - }; - - smb { - compatible = "simple-bus"; - - #address-cells = <2>; - #size-cells = <1>; - ranges = <0 0 0 0x08000000 0x04000000>, - <1 0 0 0x14000000 0x04000000>, - <2 0 0 0x18000000 0x04000000>, - <3 0 0 0x1c000000 0x04000000>, - <4 0 0 0x0c000000 0x04000000>, - <5 0 0 0x10000000 0x04000000>; - - /include/ "rtsm_ve-motherboard.dtsi" - }; - - panels { - panel@0 { - compatible = "panel"; - mode = "XVGA"; - refresh = <60>; - xres = <1024>; - yres = <768>; - pixclock = <15748>; - left_margin = <152>; - right_margin = <48>; - upper_margin = <23>; - lower_margin = <3>; - hsync_len = <104>; - vsync_len = <4>; - sync = <0>; - vmode = "FB_VMODE_NONINTERLACED"; - tim2 = "TIM2_BCD", "TIM2_IPC"; - cntl = "CNTL_LCDTFT", "CNTL_BGR", "CNTL_LCDVCOMP(1)"; - caps = "CLCD_CAP_5551", "CLCD_CAP_565", "CLCD_CAP_888"; - bpp = <16>; - }; - }; -}; +/include/ "fvp-base-gicv3-psci-common.dtsi"