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Tegra194: cleanup references to Tegra186 

This patch cleans up all references to the Tegra186 family of SoCs.

Change-Id: Ife892caba5f2523debacedf8ec465289def9afd0
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
This commit is contained in:
Varun Wadekar 2017-11-10 11:04:42 -08:00
parent ac2cc6b091
commit 1c62509e89
8 changed files with 65 additions and 127 deletions
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11
plat/nvidia/tegra/include/t194/tegra_def.h
View File

@ -30,14 +30,11 @@
/*******************************************************************************
* Secure IRQ definitions
******************************************************************************/
#define TEGRA186_MAX_SEC_IRQS U(5)
#define TEGRA186_BPMP_WDT_IRQ U(46)
#define TEGRA186_SPE_WDT_IRQ U(47)
#define TEGRA186_SCE_WDT_IRQ U(48)
#define TEGRA186_TOP_WDT_IRQ U(49)
#define TEGRA186_AON_WDT_IRQ U(50)
#define TEGRA194_MAX_SEC_IRQS U(2)
#define TEGRA194_TOP_WDT_IRQ U(49)
#define TEGRA194_AON_WDT_IRQ U(50)
#define TEGRA186_SEC_IRQ_TARGET_MASK U(0xFF) /* 8 Carmel */
#define TEGRA194_SEC_IRQ_TARGET_MASK U(0xFF) /* 8 Carmel */
/*******************************************************************************
* Tegra Miscellanous register constants

48
plat/nvidia/tegra/soc/t194/plat_psci_handlers.c
View File

@ -24,22 +24,18 @@
#include <tegra_platform.h>
#include <tegra_private.h>
extern void tegra_secure_entrypoint(void);
#if ENABLE_SYSTEM_SUSPEND_CTX_SAVE_TZDRAM
extern void tegra186_cpu_reset_handler(void);
extern uint32_t __tegra186_cpu_reset_handler_data,
__tegra186_cpu_reset_handler_end;
extern void tegra194_cpu_reset_handler(void);
extern uint32_t __tegra194_cpu_reset_handler_data,
__tegra194_cpu_reset_handler_end;
/* TZDRAM offset for saving SMMU context */
#define TEGRA186_SMMU_CTX_OFFSET 16U
#endif
#define TEGRA194_SMMU_CTX_OFFSET 16U
/* state id mask */
#define TEGRA186_STATE_ID_MASK 0xFU
#define TEGRA194_STATE_ID_MASK 0xFU
/* constants to get power state's wake time */
#define TEGRA186_WAKE_TIME_MASK 0x0FFFFFF0U
#define TEGRA186_WAKE_TIME_SHIFT 4U
#define TEGRA194_WAKE_TIME_MASK 0x0FFFFFF0U
#define TEGRA194_WAKE_TIME_SHIFT 4U
/* default core wake mask for CPU_SUSPEND */
#define TEGRA194_CORE_WAKE_MASK 0x180cU
@ -59,13 +55,13 @@ int32_t tegra_soc_validate_power_state(uint32_t power_state,
psci_power_state_t *req_state)
{
uint8_t state_id = (uint8_t)psci_get_pstate_id(power_state) &
TEGRA186_STATE_ID_MASK;
TEGRA194_STATE_ID_MASK;
uint32_t cpu = plat_my_core_pos();
int32_t ret = PSCI_E_SUCCESS;
/* save the core wake time (in TSC ticks)*/
t19x_percpu_data[cpu].wake_time = (power_state & TEGRA186_WAKE_TIME_MASK)
<< TEGRA186_WAKE_TIME_SHIFT;
t19x_percpu_data[cpu].wake_time = (power_state & TEGRA194_WAKE_TIME_MASK)
<< TEGRA194_WAKE_TIME_SHIFT;
/*
* Clean percpu_data[cpu] to DRAM. This needs to be done to ensure that
@ -101,10 +97,8 @@ int32_t tegra_soc_pwr_domain_suspend(const psci_power_state_t *target_state)
{
const plat_local_state_t *pwr_domain_state;
uint8_t stateid_afflvl0, stateid_afflvl2;
#if ENABLE_SYSTEM_SUSPEND_CTX_SAVE_TZDRAM
plat_params_from_bl2_t *params_from_bl2 = bl31_get_plat_params();
uint64_t smmu_ctx_base;
#endif
uint32_t val;
mce_cstate_info_t sc7_cstate_info = {
.cluster = (uint32_t)TEGRA_NVG_CLUSTER_CC6,
@ -118,9 +112,9 @@ int32_t tegra_soc_pwr_domain_suspend(const psci_power_state_t *target_state)
/* get the state ID */
pwr_domain_state = target_state->pwr_domain_state;
stateid_afflvl0 = pwr_domain_state[MPIDR_AFFLVL0] &
TEGRA186_STATE_ID_MASK;
TEGRA194_STATE_ID_MASK;
stateid_afflvl2 = pwr_domain_state[PLAT_MAX_PWR_LVL] &
TEGRA186_STATE_ID_MASK;
TEGRA194_STATE_ID_MASK;
if ((stateid_afflvl0 == PSTATE_ID_CORE_IDLE) ||
(stateid_afflvl0 == PSTATE_ID_CORE_POWERDN)) {
@ -138,16 +132,12 @@ int32_t tegra_soc_pwr_domain_suspend(const psci_power_state_t *target_state)
val = mmio_read_32(TEGRA_MISC_BASE + MISCREG_PFCFG);
mmio_write_32(TEGRA_SCRATCH_BASE + SCRATCH_SECURE_BOOTP_FCFG, val);
#if ENABLE_SYSTEM_SUSPEND_CTX_SAVE_TZDRAM
/* save SMMU context */
smmu_ctx_base = params_from_bl2->tzdram_base +
((uintptr_t)&__tegra186_cpu_reset_handler_data -
(uintptr_t)&tegra186_cpu_reset_handler) +
TEGRA186_SMMU_CTX_OFFSET;
((uintptr_t)&__tegra194_cpu_reset_handler_data -
(uintptr_t)&tegra194_cpu_reset_handler) +
TEGRA194_SMMU_CTX_OFFSET;
tegra_smmu_save_context((uintptr_t)smmu_ctx_base);
#else
tegra_smmu_save_context(0);
#endif
/*
* Suspend SE, RNG1 and PKA1 only on silcon and fpga,
@ -254,14 +244,13 @@ plat_local_state_t tegra_soc_get_target_pwr_state(uint32_t lvl,
return PSCI_LOCAL_STATE_RUN;
}
#if ENABLE_SYSTEM_SUSPEND_CTX_SAVE_TZDRAM
int32_t tegra_soc_pwr_domain_power_down_wfi(const psci_power_state_t *target_state)
{
const plat_local_state_t *pwr_domain_state =
target_state->pwr_domain_state;
plat_params_from_bl2_t *params_from_bl2 = bl31_get_plat_params();
uint8_t stateid_afflvl2 = pwr_domain_state[PLAT_MAX_PWR_LVL] &
TEGRA186_STATE_ID_MASK;
TEGRA194_STATE_ID_MASK;
uint64_t val;
u_register_t ns_sctlr_el1;
@ -272,8 +261,8 @@ int32_t tegra_soc_pwr_domain_power_down_wfi(const psci_power_state_t *target_sta
* BL3-1 over to TZDRAM.
*/
val = params_from_bl2->tzdram_base +
((uintptr_t)&__tegra186_cpu_reset_handler_end -
(uintptr_t)tegra186_cpu_reset_handler);
((uintptr_t)&__tegra194_cpu_reset_handler_end -
(uintptr_t)&tegra194_cpu_reset_handler);
memcpy((void *)(uintptr_t)val, (void *)(uintptr_t)BL31_BASE,
(uintptr_t)&__BL31_END__ - (uintptr_t)BL31_BASE);
@ -304,7 +293,6 @@ int32_t tegra_soc_pwr_domain_power_down_wfi(const psci_power_state_t *target_sta
return PSCI_E_SUCCESS;
}
#endif
int32_t tegra_soc_pwr_domain_on(u_register_t mpidr)
{

20
plat/nvidia/tegra/soc/t194/plat_secondary.c
View File

@ -18,12 +18,8 @@
#define CPU_RESET_MODE_AA64 1U
extern void tegra_secure_entrypoint(void);
#if ENABLE_SYSTEM_SUSPEND_CTX_SAVE_TZDRAM
extern void tegra186_cpu_reset_handler(void);
extern uint64_t __tegra186_smmu_ctx_start;
#endif
extern void tegra194_cpu_reset_handler(void);
extern uint64_t __tegra194_smmu_ctx_start;
/*******************************************************************************
* Setup secondary CPU vectors
@ -31,21 +27,15 @@ extern uint64_t __tegra186_smmu_ctx_start;
void plat_secondary_setup(void)
{
uint32_t addr_low, addr_high;
#if ENABLE_SYSTEM_SUSPEND_CTX_SAVE_TZDRAM
plat_params_from_bl2_t *params_from_bl2 = bl31_get_plat_params();
uint64_t cpu_reset_handler_base = params_from_bl2->tzdram_base;
#else
uint64_t cpu_reset_handler_base = (uintptr_t)tegra_secure_entrypoint;
#endif
INFO("Setting up secondary CPU boot\n");
#if ENABLE_SYSTEM_SUSPEND_CTX_SAVE_TZDRAM
memcpy((void *)((uintptr_t)cpu_reset_handler_base),
(void *)(uintptr_t)tegra186_cpu_reset_handler,
(uintptr_t)&__tegra186_smmu_ctx_start -
(uintptr_t)&tegra186_cpu_reset_handler);
#endif
(void *)(uintptr_t)tegra194_cpu_reset_handler,
(uintptr_t)&__tegra194_smmu_ctx_start -
(uintptr_t)&tegra194_cpu_reset_handler);
addr_low = (uint32_t)cpu_reset_handler_base | CPU_RESET_MODE_AA64;
addr_high = (uint32_t)((cpu_reset_handler_base >> 32U) & 0x7ffU);

56
plat/nvidia/tegra/soc/t194/plat_setup.c
View File

@ -122,12 +122,12 @@ uint32_t plat_get_syscnt_freq2(void)
/*******************************************************************************
* Maximum supported UART controllers
******************************************************************************/
#define TEGRA186_MAX_UART_PORTS 7
#define TEGRA194_MAX_UART_PORTS 7
/*******************************************************************************
* This variable holds the UART port base addresses
******************************************************************************/
static uint32_t tegra186_uart_addresses[TEGRA186_MAX_UART_PORTS + 1] = {
static uint32_t tegra194_uart_addresses[TEGRA194_MAX_UART_PORTS + 1] = {
0, /* undefined - treated as an error case */
TEGRA_UARTA_BASE,
TEGRA_UARTB_BASE,
@ -145,10 +145,10 @@ uint32_t plat_get_console_from_id(int32_t id)
{
uint32_t ret;
if (id > TEGRA186_MAX_UART_PORTS) {
if (id > TEGRA194_MAX_UART_PORTS) {
ret = 0;
} else {
ret = tegra186_uart_addresses[id];
ret = tegra194_uart_addresses[id];
}
return ret;
@ -212,38 +212,12 @@ void plat_early_platform_setup(void)
XUSB_PADCTL_DEV_AXI_STREAMID_PF_0, TEGRA_SID_XUSB_DEV);
}
/* Secure IRQs for Tegra186 */
static const irq_sec_cfg_t tegra186_sec_irqs[] = {
[0] = {
TEGRA186_BPMP_WDT_IRQ,
TEGRA186_SEC_IRQ_TARGET_MASK,
INTR_TYPE_EL3,
},
[1] = {
TEGRA186_BPMP_WDT_IRQ,
TEGRA186_SEC_IRQ_TARGET_MASK,
INTR_TYPE_EL3,
},
[2] = {
TEGRA186_SPE_WDT_IRQ,
TEGRA186_SEC_IRQ_TARGET_MASK,
INTR_TYPE_EL3,
},
[3] = {
TEGRA186_SCE_WDT_IRQ,
TEGRA186_SEC_IRQ_TARGET_MASK,
INTR_TYPE_EL3,
},
[4] = {
TEGRA186_TOP_WDT_IRQ,
TEGRA186_SEC_IRQ_TARGET_MASK,
INTR_TYPE_EL3,
},
[5] = {
TEGRA186_AON_WDT_IRQ,
TEGRA186_SEC_IRQ_TARGET_MASK,
INTR_TYPE_EL3,
},
/* Secure IRQs for Tegra194 */
static const interrupt_prop_t tegra194_interrupt_props[] = {
INTR_PROP_DESC(TEGRA194_TOP_WDT_IRQ, GIC_HIGHEST_SEC_PRIORITY,
GICV2_INTR_GROUP0, GIC_INTR_CFG_EDGE),
INTR_PROP_DESC(TEGRA194_AON_WDT_IRQ, GIC_HIGHEST_SEC_PRIORITY,
GICV2_INTR_GROUP0, GIC_INTR_CFG_EDGE)
};
/*******************************************************************************
@ -251,15 +225,13 @@ static const irq_sec_cfg_t tegra186_sec_irqs[] = {
******************************************************************************/
void plat_gic_setup(void)
{
tegra_gic_setup(tegra186_sec_irqs, (uint32_t)ARRAY_SIZE(tegra186_sec_irqs);
tegra_gic_setup(tegra194_interrupt_props, ARRAY_SIZE(tegra194_interrupt_props));
tegra_gic_init();
/*
* Initialize the FIQ handler only if the platform supports any
* FIQ interrupt sources.
* Initialize the FIQ handler
*/
if (sizeof(tegra186_sec_irqs) > 0U) {
tegra_fiq_handler_setup();
}
tegra_fiq_handler_setup();
}
/*******************************************************************************

4
plat/nvidia/tegra/soc/t194/plat_sip_calls.c
View File

@ -21,12 +21,12 @@
extern bool tegra_fake_system_suspend;
/*******************************************************************************
* Tegra186 SiP SMCs
* Tegra194 SiP SMCs
******************************************************************************/
#define TEGRA_SIP_ENABLE_FAKE_SYSTEM_SUSPEND 0xC2FFFE03U
/*******************************************************************************
* This function is responsible for handling all T186 SiP calls
* This function is responsible for handling all T194 SiP calls
******************************************************************************/
int32_t plat_sip_handler(uint32_t smc_fid,
uint64_t x1,

4
plat/nvidia/tegra/soc/t194/plat_smmu.c
View File

@ -20,7 +20,7 @@ static uint32_t tegra_misc_read_32(uint32_t off)
}
/*******************************************************************************
* Array to hold SMMU context for Tegra186
* Array to hold SMMU context for Tegra194
******************************************************************************/
static __attribute__((aligned(16))) smmu_regs_t tegra194_smmu_context[] = {
_START_OF_TABLE_,
@ -436,4 +436,4 @@ uint32_t plat_get_num_smmu_devices(void)
}
return ret_num;
}
}

36
plat/nvidia/tegra/soc/t194/plat_trampoline.S
View File

@ -10,13 +10,13 @@
#include <memctrl_v2.h>
#include <tegra_def.h>
#define TEGRA186_SMMU_CTX_SIZE 0x490
#define TEGRA194_SMMU_CTX_SIZE 0x490
.align 4
.globl tegra186_cpu_reset_handler
.globl tegra194_cpu_reset_handler
/* CPU reset handler routine */
func tegra186_cpu_reset_handler
func tegra194_cpu_reset_handler
/*
* The TZRAM loses state during System Suspend. We use this
* information to decide if the reset handler is running after a
@ -29,8 +29,8 @@ func tegra186_cpu_reset_handler
/* resume from system suspend */
mov x0, #BL31_BASE
adr x1, __tegra186_cpu_reset_handler_end
adr x2, __tegra186_cpu_reset_handler_data
adr x1, __tegra194_cpu_reset_handler_end
adr x2, __tegra194_cpu_reset_handler_data
ldr x2, [x2, #8]
/* memcpy16 */
@ -50,13 +50,13 @@ m_loop1:
b.ne m_loop1
boot_cpu:
adr x0, __tegra186_cpu_reset_handler_data
adr x0, __tegra194_cpu_reset_handler_data
ldr x0, [x0]
br x0
endfunc tegra186_cpu_reset_handler
endfunc tegra194_cpu_reset_handler
/*
* Tegra186 reset data (offset 0x0 - 0x2490)
* Tegra194 reset data (offset 0x0 - 0x2490)
*
* 0x0000: secure world's entrypoint
* 0x0008: BL31 size (RO + RW)
@ -65,19 +65,19 @@ endfunc tegra186_cpu_reset_handler
*/
.align 4
.type __tegra186_cpu_reset_handler_data, %object
.globl __tegra186_cpu_reset_handler_data
__tegra186_cpu_reset_handler_data:
.type __tegra194_cpu_reset_handler_data, %object
.globl __tegra194_cpu_reset_handler_data
__tegra194_cpu_reset_handler_data:
.quad tegra_secure_entrypoint
.quad __BL31_END__ - BL31_BASE
.globl __tegra186_smmu_ctx_start
__tegra186_smmu_ctx_start:
.rept TEGRA186_SMMU_CTX_SIZE
.globl __tegra194_smmu_ctx_start
__tegra194_smmu_ctx_start:
.rept TEGRA194_SMMU_CTX_SIZE
.quad 0
.endr
.size __tegra186_cpu_reset_handler_data, \
. - __tegra186_cpu_reset_handler_data
.size __tegra194_cpu_reset_handler_data, \
. - __tegra194_cpu_reset_handler_data
.align 4
.globl __tegra186_cpu_reset_handler_end
__tegra186_cpu_reset_handler_end:
.globl __tegra194_cpu_reset_handler_end
__tegra194_cpu_reset_handler_end:

13
plat/nvidia/tegra/soc/t194/platform_t194.mk
View File

@ -5,15 +5,9 @@
#
# platform configs
ENABLE_AFI_DEVICE := 0
$(eval $(call add_define,ENABLE_AFI_DEVICE))
ENABLE_ROC_FOR_ORDERING_CLIENT_REQUESTS := 0
$(eval $(call add_define,ENABLE_ROC_FOR_ORDERING_CLIENT_REQUESTS))
ENABLE_SYSTEM_SUSPEND_CTX_SAVE_TZDRAM := 1
$(eval $(call add_define,ENABLE_SYSTEM_SUSPEND_CTX_SAVE_TZDRAM))
RELOCATE_TO_BL31_BASE := 1
$(eval $(call add_define,RELOCATE_TO_BL31_BASE))
@ -60,8 +54,5 @@ BL31_SOURCES += lib/cpus/aarch64/denver.S \
${SOC_DIR}/plat_setup.c \
${SOC_DIR}/plat_secondary.c \
${SOC_DIR}/plat_sip_calls.c \
${SOC_DIR}/plat_smmu.c
ifeq (${ENABLE_SYSTEM_SUSPEND_CTX_SAVE_TZDRAM}, 1)
BL31_SOURCES += ${SOC_DIR}/plat_trampoline.S
endif
${SOC_DIR}/plat_smmu.c \
${SOC_DIR}/plat_trampoline.S