feat(drivers/arm/ethosn)!: multi-device support
Add support for Arm Ethos-N NPU multi-device. The device tree parsing currently only supports one NPU device with multiple cores. To be able to support multi-device NPU configurations this patch adds support for having multiple NPU devices in the device tree. To be able to support multiple NPU devices in the SMC API, it has been changed in an incompatible way so the API version has been bumped. Signed-off-by: Laurent Carlier <laurent.carlier@arm.com> Change-Id: Ide279ce949bd06e8939268b9601c267e45f3edc3
This commit is contained in:
Laurent Carlier
parent
ff766148b5
commit
1c65989e70
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@ -14,11 +14,10 @@
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#include <lib/mmio.h>
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#include <plat/arm/common/fconf_ethosn_getter.h>
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/* Arm Ethos-N NPU (NPU) status */
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#define ETHOSN_STATUS \
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FCONF_GET_PROPERTY(hw_config, ethosn_config, status)
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/* Number of NPU cores available */
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/*
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* Number of Arm Ethos-N NPU (NPU) cores available for a
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* particular parent device
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*/
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#define ETHOSN_NUM_CORES \
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FCONF_GET_PROPERTY(hw_config, ethosn_config, num_cores)
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@ -51,6 +50,17 @@
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#define SEC_SYSCTRL0_SOFT_RESET U(3U << 29)
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#define SEC_SYSCTRL0_HARD_RESET U(1U << 31)
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static bool ethosn_is_core_addr_valid(uintptr_t core_addr)
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{
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for (uint32_t core_idx = 0U; core_idx < ETHOSN_NUM_CORES; core_idx++) {
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if (ETHOSN_CORE_ADDR(core_idx) == core_addr) {
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return true;
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}
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}
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return false;
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}
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static void ethosn_delegate_to_ns(uintptr_t core_addr)
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{
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mmio_setbits_32(ETHOSN_CORE_SEC_REG(core_addr, SEC_SECCTLR_REG),
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@ -66,9 +76,9 @@ static void ethosn_delegate_to_ns(uintptr_t core_addr)
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SEC_DEL_ADDR_EXT_VAL);
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}
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static int ethosn_is_sec(void)
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static int ethosn_is_sec(uintptr_t core_addr)
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{
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if ((mmio_read_32(ETHOSN_CORE_SEC_REG(ETHOSN_CORE_ADDR(0), SEC_DEL_REG))
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if ((mmio_read_32(ETHOSN_CORE_SEC_REG(core_addr, SEC_DEL_REG))
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& SEC_DEL_EXCC_MASK) != 0U) {
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return 0;
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}
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@ -101,7 +111,7 @@ static bool ethosn_reset(uintptr_t core_addr, int hard_reset)
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}
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uintptr_t ethosn_smc_handler(uint32_t smc_fid,
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u_register_t core_idx,
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u_register_t core_addr,
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u_register_t x2,
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u_register_t x3,
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u_register_t x4,
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@ -109,8 +119,8 @@ uintptr_t ethosn_smc_handler(uint32_t smc_fid,
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void *handle,
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u_register_t flags)
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{
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uintptr_t core_addr;
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int hard_reset = 0;
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const uint32_t fid = smc_fid & FUNCID_NUM_MASK;
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/* Only SiP fast calls are expected */
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if ((GET_SMC_TYPE(smc_fid) != SMC_TYPE_FAST) ||
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@ -120,7 +130,7 @@ uintptr_t ethosn_smc_handler(uint32_t smc_fid,
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/* Truncate parameters to 32-bits for SMC32 */
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if (GET_SMC_CC(smc_fid) == SMC_32) {
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core_idx &= 0xFFFFFFFF;
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core_addr &= 0xFFFFFFFF;
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x2 &= 0xFFFFFFFF;
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x3 &= 0xFFFFFFFF;
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x4 &= 0xFFFFFFFF;
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@ -130,33 +140,29 @@ uintptr_t ethosn_smc_handler(uint32_t smc_fid,
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SMC_RET1(handle, SMC_UNK);
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}
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if (ETHOSN_STATUS == ETHOSN_STATUS_DISABLED) {
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WARN("ETHOSN: Arm Ethos-N NPU not available\n");
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SMC_RET1(handle, ETHOSN_NOT_SUPPORTED);
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}
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switch (smc_fid & FUNCID_NUM_MASK) {
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/* Commands that do not require a valid core address */
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switch (fid) {
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case ETHOSN_FNUM_VERSION:
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SMC_RET2(handle, ETHOSN_VERSION_MAJOR, ETHOSN_VERSION_MINOR);
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}
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if (!ethosn_is_core_addr_valid(core_addr)) {
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WARN("ETHOSN: Unknown core address given to SMC call.\n");
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SMC_RET1(handle, ETHOSN_UNKNOWN_CORE_ADDRESS);
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}
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/* Commands that require a valid addr */
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switch (fid) {
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case ETHOSN_FNUM_IS_SEC:
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SMC_RET1(handle, ethosn_is_sec());
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SMC_RET1(handle, ethosn_is_sec(core_addr));
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case ETHOSN_FNUM_HARD_RESET:
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hard_reset = 1;
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/* Fallthrough */
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case ETHOSN_FNUM_SOFT_RESET:
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if (core_idx >= ETHOSN_NUM_CORES) {
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WARN("ETHOSN: core index out of range\n");
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SMC_RET1(handle, ETHOSN_CORE_IDX_OUT_OF_RANGE);
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}
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core_addr = ETHOSN_CORE_ADDR(core_idx);
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if (!ethosn_reset(core_addr, hard_reset)) {
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SMC_RET1(handle, ETHOSN_FAILURE);
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}
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ethosn_delegate_to_ns(core_addr);
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SMC_RET1(handle, ETHOSN_SUCCESS);
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default:
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SMC_RET1(handle, SMC_UNK);
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@ -4,19 +4,21 @@
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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/*
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* For examples of multi-core and multi-device NPU, refer to the examples given in the
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* Arm Ethos-N NPU driver stack.
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* https://github.com/ARM-software/ethos-n-driver-stack
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*/
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/ {
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#address-cells = <2>;
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#size-cells = <2>;
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ethosn: ethosn@6f300000 {
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ethosn0: ethosn@6f300000 {
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compatible = "ethosn";
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reg = <0 0x6f300000 0 0x00100000>;
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status = "okay";
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/*
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* Single-core NPU. For multi-core NPU, additional core nodes
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* and reg values must be added.
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*/
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core0 {
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compatible = "ethosn-core";
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status = "okay";
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@ -38,8 +38,8 @@
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#define is_ethosn_fid(_fid) (((_fid) & ETHOSN_FID_MASK) == ETHOSN_FID_VALUE)
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/* Service version */
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#define ETHOSN_VERSION_MAJOR U(0)
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#define ETHOSN_VERSION_MINOR U(1)
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#define ETHOSN_VERSION_MAJOR U(1)
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#define ETHOSN_VERSION_MINOR U(0)
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/* Return codes for function calls */
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#define ETHOSN_SUCCESS 0
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@ -47,10 +47,10 @@
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/* -2 Reserved for NOT_REQUIRED */
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/* -3 Reserved for INVALID_PARAMETER */
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#define ETHOSN_FAILURE -4
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#define ETHOSN_CORE_IDX_OUT_OF_RANGE -5
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#define ETHOSN_UNKNOWN_CORE_ADDRESS -5
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uintptr_t ethosn_smc_handler(uint32_t smc_fid,
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u_register_t core_idx,
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u_register_t core_addr,
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u_register_t x2,
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u_register_t x3,
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u_register_t x4,
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@ -14,7 +14,7 @@
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#define hw_config__ethosn_config_getter(prop) ethosn_config.prop
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#define hw_config__ethosn_core_addr_getter(idx) __extension__ ({ \
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assert(idx < ethosn_config.num_cores); \
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ethosn_config.core_addr[idx]; \
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ethosn_config.core[idx].addr; \
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})
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#define ETHOSN_STATUS_DISABLED U(0)
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@ -22,10 +22,13 @@
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#define ETHOSN_CORE_NUM_MAX U(64)
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struct ethosn_core_t {
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uint64_t addr;
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};
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struct ethosn_config_t {
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uint8_t status;
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uint32_t num_cores;
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uint64_t core_addr[ETHOSN_CORE_NUM_MAX];
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struct ethosn_core_t core[ETHOSN_CORE_NUM_MAX];
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};
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int fconf_populate_arm_ethosn(uintptr_t config);
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@ -12,7 +12,7 @@
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#include <libfdt.h>
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#include <plat/arm/common/fconf_ethosn_getter.h>
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struct ethosn_config_t ethosn_config;
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struct ethosn_config_t ethosn_config = {.num_cores = 0};
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static uint8_t fdt_node_get_status(const void *fdt, int node)
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{
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@ -33,74 +33,86 @@ static uint8_t fdt_node_get_status(const void *fdt, int node)
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int fconf_populate_ethosn_config(uintptr_t config)
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{
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int ethosn_node;
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int sub_node;
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uint8_t ethosn_status;
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uint32_t core_count = 0U;
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uint32_t core_addr_idx = 0U;
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const void *hw_conf_dtb = (const void *)config;
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/* Find offset to node with 'ethosn' compatible property */
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ethosn_node = fdt_node_offset_by_compatible(hw_conf_dtb, -1, "ethosn");
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if (ethosn_node < 0) {
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INFO("Probing Arm Ethos-N NPU\n");
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uint32_t total_core_count = 0U;
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fdt_for_each_compatible_node(hw_conf_dtb, ethosn_node, "ethosn") {
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int sub_node;
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uint8_t ethosn_status;
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uint32_t device_core_count = 0U;
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/* If the Arm Ethos-N NPU is disabled the core check can be skipped */
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ethosn_status = fdt_node_get_status(hw_conf_dtb, ethosn_node);
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if (ethosn_status == ETHOSN_STATUS_DISABLED) {
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continue;
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}
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fdt_for_each_subnode(sub_node, hw_conf_dtb, ethosn_node) {
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int err;
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uintptr_t core_addr;
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uint8_t core_status;
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if (total_core_count >= ETHOSN_CORE_NUM_MAX) {
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ERROR("FCONF: Reached max number of Arm Ethos-N NPU cores\n");
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return -FDT_ERR_BADSTRUCTURE;
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}
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/* Check that the sub node is "ethosn-core" compatible */
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if (fdt_node_check_compatible(hw_conf_dtb,
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sub_node,
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"ethosn-core") != 0) {
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/* Ignore incompatible sub node */
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continue;
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}
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core_status = fdt_node_get_status(hw_conf_dtb, sub_node);
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if (core_status == ETHOSN_STATUS_DISABLED) {
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continue;
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}
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err = fdt_get_reg_props_by_index(hw_conf_dtb,
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ethosn_node,
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device_core_count,
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&core_addr,
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NULL);
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if (err < 0) {
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ERROR(
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"FCONF: Failed to read reg property for Arm Ethos-N NPU core %u\n",
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device_core_count);
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return err;
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}
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INFO("NPU core probed at address 0x%lx\n", core_addr);
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ethosn_config.core[total_core_count].addr = core_addr;
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total_core_count++;
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device_core_count++;
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}
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if ((sub_node < 0) && (sub_node != -FDT_ERR_NOTFOUND)) {
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ERROR("FCONF: Failed to parse sub nodes\n");
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return -FDT_ERR_BADSTRUCTURE;
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}
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if (device_core_count == 0U) {
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ERROR(
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"FCONF: Enabled Arm Ethos-N NPU device must have at least one enabled core\n");
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return -FDT_ERR_BADSTRUCTURE;
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}
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}
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if (total_core_count == 0U) {
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ERROR("FCONF: Can't find 'ethosn' compatible node in dtb\n");
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return ethosn_node;
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return -FDT_ERR_BADSTRUCTURE;
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}
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/* If the Arm Ethos-N NPU is disabled the core check can be skipped */
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ethosn_status = fdt_node_get_status(hw_conf_dtb, ethosn_node);
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if (ethosn_status == ETHOSN_STATUS_DISABLED) {
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return 0;
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}
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ethosn_config.num_cores = total_core_count;
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fdt_for_each_subnode(sub_node, hw_conf_dtb, ethosn_node) {
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int err;
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uintptr_t addr;
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uint8_t status;
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/* Check that the sub node is "ethosn-core" compatible */
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if (fdt_node_check_compatible(hw_conf_dtb, sub_node,
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"ethosn-core") != 0) {
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/* Ignore incompatible sub node */
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continue;
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}
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/* Including disabled cores */
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if (core_addr_idx >= ETHOSN_CORE_NUM_MAX) {
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ERROR("FCONF: Reached max number of Arm Ethos-N NPU cores\n");
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return -1;
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}
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status = fdt_node_get_status(hw_conf_dtb, ethosn_node);
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if (status == ETHOSN_STATUS_DISABLED) {
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++core_addr_idx;
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continue;
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}
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err = fdt_get_reg_props_by_index(hw_conf_dtb, ethosn_node,
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core_addr_idx, &addr, NULL);
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if (err < 0) {
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ERROR("FCONF: Failed to read reg property for Arm Ethos-N NPU core %u\n",
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core_addr_idx);
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return err;
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}
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ethosn_config.core_addr[core_count++] = addr;
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++core_addr_idx;
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}
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if ((sub_node < 0) && (sub_node != -FDT_ERR_NOTFOUND)) {
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ERROR("FCONF: Failed to parse sub nodes\n");
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return sub_node;
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}
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/* The Arm Ethos-N NPU can't be used if no cores were found */
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if (core_count == 0) {
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ERROR("FCONF: No Arm Ethos-N NPU cores found\n");
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return -1;
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}
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ethosn_config.num_cores = core_count;
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ethosn_config.status = ethosn_status;
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INFO("%d NPU core%s probed\n",
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ethosn_config.num_cores,
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ethosn_config.num_cores > 1 ? "s" : "");
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return 0;
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}
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