Tegra: platform dependent address space sizes
This patch moves the PLAT_PHY_ADDR_SPACE_SIZE & PLAT_VIRT_ADDR_SPACE macros to tegra_def.h, to define the virtual/physical address space size on the platform. Change-Id: I1c5d264c7ffc1af0e7b14cc16ae2c0416efc76f6 Signed-off-by: Steven Kao <skao@nvidia.com>
This commit is contained in:
parent
26cf08494b
commit
1d11f73e58
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
|
||||
* Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
@ -53,12 +53,6 @@
|
|||
#define BL32_BASE (TZDRAM_BASE + BL31_SIZE)
|
||||
#define BL32_LIMIT TZDRAM_END
|
||||
|
||||
/*******************************************************************************
|
||||
* Platform specific page table and MMU setup constants
|
||||
******************************************************************************/
|
||||
#define PLAT_PHY_ADDR_SPACE_SIZE (ULL(1) << 35)
|
||||
#define PLAT_VIRT_ADDR_SPACE_SIZE (ULL(1) << 35)
|
||||
|
||||
/*******************************************************************************
|
||||
* Some data must be aligned on the biggest cache line size in the platform.
|
||||
* This is known only to the platform as it might have a combination of
|
||||
|
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
|
||||
* Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
@ -24,6 +24,12 @@
|
|||
#define PLAT_MAX_RET_STATE U(1)
|
||||
#define PLAT_MAX_OFF_STATE (PSTATE_ID_SOC_POWERDN + U(1))
|
||||
|
||||
/*******************************************************************************
|
||||
* Chip specific page table and MMU setup constants
|
||||
******************************************************************************/
|
||||
#define PLAT_PHY_ADDR_SPACE_SIZE (ULL(1) << 35)
|
||||
#define PLAT_VIRT_ADDR_SPACE_SIZE (ULL(1) << 35)
|
||||
|
||||
/*******************************************************************************
|
||||
* GIC memory map
|
||||
******************************************************************************/
|
||||
|
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
|
||||
* Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
@ -57,6 +57,12 @@
|
|||
#define PLAT_MAX_RET_STATE U(1)
|
||||
#define PLAT_MAX_OFF_STATE U(8)
|
||||
|
||||
/*******************************************************************************
|
||||
* Chip specific page table and MMU setup constants
|
||||
******************************************************************************/
|
||||
#define PLAT_PHY_ADDR_SPACE_SIZE (ULL(1) << 35)
|
||||
#define PLAT_VIRT_ADDR_SPACE_SIZE (ULL(1) << 35)
|
||||
|
||||
/*******************************************************************************
|
||||
* Secure IRQ definitions
|
||||
******************************************************************************/
|
||||
|
|
|
@ -32,6 +32,12 @@
|
|||
#define PLAT_MAX_RET_STATE U(1)
|
||||
#define PLAT_MAX_OFF_STATE (PSTATE_ID_SOC_POWERDN + U(1))
|
||||
|
||||
/*******************************************************************************
|
||||
* Chip specific page table and MMU setup constants
|
||||
******************************************************************************/
|
||||
#define PLAT_PHY_ADDR_SPACE_SIZE (ULL(1) << 35)
|
||||
#define PLAT_VIRT_ADDR_SPACE_SIZE (ULL(1) << 35)
|
||||
|
||||
/*******************************************************************************
|
||||
* iRAM memory constants
|
||||
******************************************************************************/
|
||||
|
|
Loading…
Reference in New Issue