hikey: save ddr parameters into SRAM
Store those DDR parameters into SRAM. They may be used by MCU firmware. Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
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@ -10,6 +10,7 @@
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#include <errno.h>
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#include <hi6220.h>
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#include <hi6553.h>
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#include <hisi_sram_map.h>
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#include <mmio.h>
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#include <sp804_delay_timer.h>
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@ -1137,20 +1138,24 @@ static int dienum_det_and_rowcol_cfg(void)
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mmio_write_32((0xf7128000 + 0x064), 0x132);
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mmio_write_32((0xf7120000 + 0x100), 0x1600);
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mmio_write_32((0xf7120000 + 0x104), 0x71040004);
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mmio_write_32(MEMORY_AXI_DDR_CAPACITY_ADDR, 0x40000000);
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break;
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case 0x1c:
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mmio_write_32((0xf7128000 + 0x060), 0x142);
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mmio_write_32((0xf7128000 + 0x064), 0x142);
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mmio_write_32((0xf7120000 + 0x100), 0x1700);
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mmio_write_32((0xf7120000 + 0x104), 0x71040004);
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mmio_write_32(MEMORY_AXI_DDR_CAPACITY_ADDR, 0x80000000);
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break;
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case 0x58:
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mmio_write_32((0xf7128000 + 0x060), 0x133);
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mmio_write_32((0xf7128000 + 0x064), 0x133);
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mmio_write_32((0xf7120000 + 0x100), 0x1700);
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mmio_write_32((0xf7120000 + 0x104), 0x71040004);
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mmio_write_32(MEMORY_AXI_DDR_CAPACITY_ADDR, 0x80000000);
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break;
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default:
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mmio_write_32(MEMORY_AXI_DDR_CAPACITY_ADDR, 0x80000000);
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break;
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}
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if (!data)
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@ -1213,24 +1218,107 @@ void ddr_phy_reset(void)
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mmio_write_32(0xf7030344, 0xa000);
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}
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void lpddrx_save_ddl_para_bypass(uint32_t *ddr_ddl_para, unsigned int index)
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{
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uint32_t value;
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uint32_t cnt = index;
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uint32_t i;
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for (i = 0; i < 4; i++) {
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value = mmio_read_32(0xf712c000 + 0x22c + i * 0x80);
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ddr_ddl_para[cnt++] = value;
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value = mmio_read_32(0xf712c000 + 0x23c + i * 0x80);
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ddr_ddl_para[cnt++] = value;
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value = mmio_read_32(0xf712c000 + 0x240 + i * 0x80);
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ddr_ddl_para[cnt++] = value;
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value = mmio_read_32(0xf712c000 + 0x640 + i * 0x80);
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ddr_ddl_para[cnt++] = value;
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}
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}
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void lpddrx_save_ddl_para_mission(uint32_t *ddr_ddl_para, unsigned int index)
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{
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uint32_t value;
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uint32_t cnt = index;
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uint32_t i;
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value = mmio_read_32(0xf712c000 + 0x140);
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ddr_ddl_para[cnt++] = value;
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value = mmio_read_32(0xf712c000 + 0x144);
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ddr_ddl_para[cnt++] = value;
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value = mmio_read_32(0xf712c000 + 0x148);
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ddr_ddl_para[cnt++] = value;
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value = mmio_read_32(0xf712c000 + 0x14c);
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ddr_ddl_para[cnt++] = value;
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value = mmio_read_32(0xf712c000 + 0x150);
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ddr_ddl_para[cnt++] = value;
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value = mmio_read_32(0xf712c000 + 0x1d4);
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ddr_ddl_para[cnt++] = value;
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for (i = 0; i < 4; i++) {
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value = mmio_read_32(0xf712c000 + 0x210 + i * 0x80);
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ddr_ddl_para[cnt++] = value;
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value = mmio_read_32(0xf712c000 + 0x214 + i * 0x80);
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ddr_ddl_para[cnt++] = value;
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value = mmio_read_32(0xf712c000 + 0x218 + i * 0x80);
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ddr_ddl_para[cnt++] = value;
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value = mmio_read_32(0xf712c000 + 0x21c + i * 0x80);
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ddr_ddl_para[cnt++] = value;
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value = mmio_read_32(0xf712c000 + 0x220 + i * 0x80);
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ddr_ddl_para[cnt++] = value;
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value = mmio_read_32(0xf712c000 + 0x224 + i * 0x80);
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ddr_ddl_para[cnt++] = value;
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value = mmio_read_32(0xf712c000 + 0x228 + i * 0x80);
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ddr_ddl_para[cnt++] = value;
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value = mmio_read_32(0xf712c000 + 0x22c + i * 0x80);
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ddr_ddl_para[cnt++] = value;
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value = mmio_read_32(0xf712c000 + 0x230 + i * 0x80);
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ddr_ddl_para[cnt++] = value;
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value = mmio_read_32(0xf712c000 + 0x234 + i * 0x80);
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ddr_ddl_para[cnt++] = value;
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value = mmio_read_32(0xf712c000 + 0x238 + i * 0x80);
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ddr_ddl_para[cnt++] = value;
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value = mmio_read_32(0xf712c000 + 0x23c + i * 0x80);
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ddr_ddl_para[cnt++] = value;
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value = mmio_read_32(0xf712c000 + 0x240 + i * 0x80);
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ddr_ddl_para[cnt++] = value;
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value = mmio_read_32(0xf712c000 + 0x640 + i * 0x80);
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ddr_ddl_para[cnt++] = value;
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}
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value = mmio_read_32(0xf712c000 + 0x168);
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ddr_ddl_para[cnt++] = value;
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value = mmio_read_32(0xf712c000 + 0x24c + 0 * 0x80);
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ddr_ddl_para[cnt++] = value;
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value = mmio_read_32(0xf712c000 + 0x24c + 2 * 0x80);
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ddr_ddl_para[cnt++] = value;
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}
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int lpddr3_freq_init(int freq)
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{
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set_ddrc_150mhz();
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lpddrx_save_ddl_para_bypass((uint32_t *)MEMORY_AXI_DDR_DDL_ADDR, 0);
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if (freq > DDR_FREQ_150M) {
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ddr_phy_reset();
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set_ddrc_266mhz();
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lpddrx_save_ddl_para_bypass((uint32_t *)MEMORY_AXI_DDR_DDL_ADDR,
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16);
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}
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if (freq > DDR_FREQ_266M) {
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ddr_phy_reset();
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set_ddrc_400mhz();
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lpddrx_save_ddl_para_bypass((uint32_t *)MEMORY_AXI_DDR_DDL_ADDR,
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16 * 2);
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}
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if (freq > DDR_FREQ_400M) {
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ddr_phy_reset();
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set_ddrc_533mhz();
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lpddrx_save_ddl_para_mission((uint32_t *)MEMORY_AXI_DDR_DDL_ADDR,
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16 * 3);
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}
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if (freq > DDR_FREQ_533M) {
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ddr_phy_reset();
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set_ddrc_800mhz();
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lpddrx_save_ddl_para_mission((uint32_t *)MEMORY_AXI_DDR_DDL_ADDR,
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16 * 3 + 61);
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}
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return 0;
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}
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