Merge changes from topic "tp-feat-rng" into integration
* changes: plat/qemu: Use RNDR in stack protector Makefile: Add FEAT_RNG support define Define registers for FEAT_RNG support
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1ddf38e853
5
Makefile
5
Makefile
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@ -242,6 +242,9 @@ endif
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$(info Arm Architecture Features specified: $(subst +, ,$(arch-features)))
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$(info Arm Architecture Features specified: $(subst +, ,$(arch-features)))
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endif # arch-features
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endif # arch-features
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# Determine if FEAT_RNG is supported
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ENABLE_FEAT_RNG = $(if $(findstring rng,${arch-features}),1,0)
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ifneq ($(findstring armclang,$(notdir $(CC))),)
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ifneq ($(findstring armclang,$(notdir $(CC))),)
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TF_CFLAGS_aarch32 = -target arm-arm-none-eabi $(march32-directive)
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TF_CFLAGS_aarch32 = -target arm-arm-none-eabi $(march32-directive)
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TF_CFLAGS_aarch64 = -target aarch64-arm-none-eabi $(march64-directive)
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TF_CFLAGS_aarch64 = -target aarch64-arm-none-eabi $(march64-directive)
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@ -940,6 +943,7 @@ $(eval $(call assert_booleans,\
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RAS_TRAP_LOWER_EL_ERR_ACCESS \
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RAS_TRAP_LOWER_EL_ERR_ACCESS \
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COT_DESC_IN_DTB \
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COT_DESC_IN_DTB \
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USE_SP804_TIMER \
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USE_SP804_TIMER \
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ENABLE_FEAT_RNG \
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)))
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)))
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$(eval $(call assert_numerics,\
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$(eval $(call assert_numerics,\
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@ -1030,6 +1034,7 @@ $(eval $(call add_defines,\
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RAS_TRAP_LOWER_EL_ERR_ACCESS \
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RAS_TRAP_LOWER_EL_ERR_ACCESS \
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COT_DESC_IN_DTB \
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COT_DESC_IN_DTB \
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USE_SP804_TIMER \
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USE_SP804_TIMER \
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ENABLE_FEAT_RNG \
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)))
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)))
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ifeq (${SANITIZE_UB},trap)
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ifeq (${SANITIZE_UB},trap)
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@ -193,6 +193,10 @@
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#define ID_AA64DFR0_MTPMU_MASK ULL(0xf)
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#define ID_AA64DFR0_MTPMU_MASK ULL(0xf)
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#define ID_AA64DFR0_MTPMU_SUPPORTED ULL(1)
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#define ID_AA64DFR0_MTPMU_SUPPORTED ULL(1)
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/* ID_AA64ISAR0_EL1 definitions */
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#define ID_AA64ISAR0_RNDR_SHIFT U(60)
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#define ID_AA64ISAR0_RNDR_MASK ULL(0xf)
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/* ID_AA64ISAR1_EL1 definitions */
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/* ID_AA64ISAR1_EL1 definitions */
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#define ID_AA64ISAR1_EL1 S3_0_C0_C6_1
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#define ID_AA64ISAR1_EL1 S3_0_C0_C6_1
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#define ID_AA64ISAR1_GPI_SHIFT U(28)
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#define ID_AA64ISAR1_GPI_SHIFT U(28)
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@ -76,6 +76,12 @@ static inline unsigned long int get_armv8_6_ecv_support(void)
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ID_AA64MMFR0_EL1_ECV_MASK);
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ID_AA64MMFR0_EL1_ECV_MASK);
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}
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}
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static inline bool is_armv8_5_rng_present(void)
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{
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return ((read_id_aa64isar0_el1() >> ID_AA64ISAR0_RNDR_SHIFT) &
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ID_AA64ISAR0_RNDR_MASK);
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}
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/*
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/*
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* Return MPAM version:
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* Return MPAM version:
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*
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*
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@ -245,6 +245,7 @@ void disable_mmu_icache_el3(void);
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DEFINE_SYSREG_RW_FUNCS(par_el1)
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DEFINE_SYSREG_RW_FUNCS(par_el1)
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DEFINE_SYSREG_READ_FUNC(id_pfr1_el1)
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DEFINE_SYSREG_READ_FUNC(id_pfr1_el1)
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DEFINE_SYSREG_READ_FUNC(id_aa64isar0_el1)
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DEFINE_SYSREG_READ_FUNC(id_aa64isar1_el1)
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DEFINE_SYSREG_READ_FUNC(id_aa64isar1_el1)
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DEFINE_SYSREG_READ_FUNC(id_aa64pfr0_el1)
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DEFINE_SYSREG_READ_FUNC(id_aa64pfr0_el1)
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DEFINE_SYSREG_READ_FUNC(id_aa64pfr1_el1)
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DEFINE_SYSREG_READ_FUNC(id_aa64pfr1_el1)
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@ -522,6 +523,10 @@ DEFINE_RENAME_SYSREG_RW_FUNCS(tfsr_el1, TFSR_EL1)
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DEFINE_RENAME_SYSREG_RW_FUNCS(rgsr_el1, RGSR_EL1)
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DEFINE_RENAME_SYSREG_RW_FUNCS(rgsr_el1, RGSR_EL1)
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DEFINE_RENAME_SYSREG_RW_FUNCS(gcr_el1, GCR_EL1)
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DEFINE_RENAME_SYSREG_RW_FUNCS(gcr_el1, GCR_EL1)
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/* Armv8.5 FEAT_RNG Registers */
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DEFINE_SYSREG_READ_FUNC(rndr)
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DEFINE_SYSREG_READ_FUNC(rndrrs)
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/* DynamIQ Shared Unit power management */
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/* DynamIQ Shared Unit power management */
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DEFINE_RENAME_SYSREG_RW_FUNCS(clusterpwrdn_el1, CLUSTERPWRDN_EL1)
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DEFINE_RENAME_SYSREG_RW_FUNCS(clusterpwrdn_el1, CLUSTERPWRDN_EL1)
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@ -1,5 +1,5 @@
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/*
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/*
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* Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2021, ARM Limited and Contributors. All rights reserved.
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*
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*
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* SPDX-License-Identifier: BSD-3-Clause
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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*/
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@ -7,17 +7,25 @@
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#include <stdint.h>
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#include <stdint.h>
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#include <arch_helpers.h>
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#include <arch_helpers.h>
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#include <arch_features.h>
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#include <plat/common/platform.h>
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#include <plat/common/platform.h>
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#define RANDOM_CANARY_VALUE ((u_register_t) 3288484550995823360ULL)
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#define RANDOM_CANARY_VALUE ((u_register_t) 3288484550995823360ULL)
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u_register_t plat_get_stack_protector_canary(void)
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u_register_t plat_get_stack_protector_canary(void)
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{
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{
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#if ENABLE_FEAT_RNG
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/* Use the RNDR instruction if the CPU supports it */
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if (is_armv8_5_rng_present()) {
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return read_rndr();
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}
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#endif
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/*
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/*
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* Ideally, a random number should be returned instead of the
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* Ideally, a random number should be returned above. If a random
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* number generator is not supported, return instead a
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* combination of a timer's value and a compile-time constant.
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* combination of a timer's value and a compile-time constant.
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* As the virt platform does not have any random number generator,
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* This is better than nothing but not necessarily really secure.
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* this is better than nothing but not necessarily really secure.
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*/
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*/
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return RANDOM_CANARY_VALUE ^ read_cntpct_el0();
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return RANDOM_CANARY_VALUE ^ read_cntpct_el0();
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}
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}
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