Tegra186: Enable ECC and Parity Protection for A02p SKUs
This patch enables ECC and Parity Protection for Cortex-A57 CPUs during boot, for Tegra186 A02p SKUs. Change-Id: I8522a6cb61f5e4fa9e0471f558a0c3ee8078370e Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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@ -105,6 +105,13 @@
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#define TEGRA_UARTF_BASE 0x03150000
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#define TEGRA_UARTF_BASE 0x03150000
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#define TEGRA_UARTG_BASE 0x0C290000
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#define TEGRA_UARTG_BASE 0x0C290000
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/*******************************************************************************
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* Tegra Fuse Controller related constants
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******************************************************************************/
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#define TEGRA_FUSE_BASE 0x03820000
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#define OPT_SUBREVISION 0x248
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#define SUBREVISION_MASK 0xFF
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/*******************************************************************************
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/*******************************************************************************
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* GICv2 & interrupt handling related constants
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* GICv2 & interrupt handling related constants
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******************************************************************************/
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******************************************************************************/
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@ -34,6 +34,7 @@
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#include <console.h>
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#include <console.h>
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#include <context.h>
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#include <context.h>
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#include <context_mgmt.h>
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#include <context_mgmt.h>
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#include <cortex_a57.h>
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#include <debug.h>
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#include <debug.h>
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#include <denver.h>
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#include <denver.h>
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#include <interrupt_mgmt.h>
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#include <interrupt_mgmt.h>
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@ -43,6 +44,9 @@
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#include <tegra_private.h>
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#include <tegra_private.h>
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#include <xlat_tables.h>
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#include <xlat_tables.h>
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DEFINE_RENAME_SYSREG_RW_FUNCS(l2ctlr_el1, L2CTLR_EL1)
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extern uint64_t tegra_enable_l2_ecc_parity_prot;
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/*******************************************************************************
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/*******************************************************************************
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* The Tegra power domain tree has a single system level power domain i.e. a
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* The Tegra power domain tree has a single system level power domain i.e. a
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* single root node. The first entry in the power domain descriptor specifies
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* single root node. The first entry in the power domain descriptor specifies
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@ -74,6 +78,8 @@ static const mmap_region_t tegra_mmap[] = {
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MT_DEVICE | MT_RW | MT_SECURE),
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MT_DEVICE | MT_RW | MT_SECURE),
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MAP_REGION_FLAT(TEGRA_UARTA_BASE, 0x20000, /* 128KB */
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MAP_REGION_FLAT(TEGRA_UARTA_BASE, 0x20000, /* 128KB */
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MT_DEVICE | MT_RW | MT_SECURE),
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MT_DEVICE | MT_RW | MT_SECURE),
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MAP_REGION_FLAT(TEGRA_FUSE_BASE, 0x10000, /* 64KB */
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MT_DEVICE | MT_RW | MT_SECURE),
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MAP_REGION_FLAT(TEGRA_GICD_BASE, 0x20000, /* 128KB */
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MAP_REGION_FLAT(TEGRA_GICD_BASE, 0x20000, /* 128KB */
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MT_DEVICE | MT_RW | MT_SECURE),
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MT_DEVICE | MT_RW | MT_SECURE),
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MAP_REGION_FLAT(TEGRA_SE0_BASE, 0x10000, /* 64KB */
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MAP_REGION_FLAT(TEGRA_SE0_BASE, 0x10000, /* 64KB */
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@ -142,6 +148,55 @@ uint32_t plat_get_console_from_id(int id)
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return tegra186_uart_addresses[id];
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return tegra186_uart_addresses[id];
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}
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}
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/* represent chip-version as concatenation of major (15:12), minor (11:8) and subrev (7:0) */
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#define TEGRA186_VER_A02P 0x1201
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/*******************************************************************************
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* Handler for early platform setup
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******************************************************************************/
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void plat_early_platform_setup(void)
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{
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int impl = (read_midr() >> MIDR_IMPL_SHIFT) & MIDR_IMPL_MASK;
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uint32_t chip_minor, chip_major, chip_subrev, val;
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/* sanity check MCE firmware compatibility */
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mce_verify_firmware_version();
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/*
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* Enable ECC and Parity Protection for Cortex-A57 CPUs
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* for Tegra A02p SKUs
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*/
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if (impl != DENVER_IMPL) {
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/* get the major, minor and sub-version values */
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chip_major = (mmio_read_32(TEGRA_MISC_BASE +
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HARDWARE_REVISION_OFFSET) >>
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MAJOR_VERSION_SHIFT) & MAJOR_VERSION_MASK;
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chip_minor = (mmio_read_32(TEGRA_MISC_BASE +
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HARDWARE_REVISION_OFFSET) >>
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MINOR_VERSION_SHIFT) & MINOR_VERSION_MASK;
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chip_subrev = mmio_read_32(TEGRA_FUSE_BASE + OPT_SUBREVISION) &
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SUBREVISION_MASK;
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/* prepare chip version number */
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val = (chip_major << 12) | (chip_minor << 8) | chip_subrev;
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/* enable L2 ECC for Tegra186 A02P and beyond */
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if (val >= TEGRA186_VER_A02P) {
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val = read_l2ctlr_el1();
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val |= L2_ECC_PARITY_PROTECTION_BIT;
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write_l2ctlr_el1(val);
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/*
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* Set the flag to enable ECC/Parity Protection
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* when we exit System Suspend or Cluster Powerdn
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*/
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tegra_enable_l2_ecc_parity_prot = 1;
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}
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}
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}
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/* Secure IRQs for Tegra186 */
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/* Secure IRQs for Tegra186 */
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static const irq_sec_cfg_t tegra186_sec_irqs[] = {
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static const irq_sec_cfg_t tegra186_sec_irqs[] = {
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{
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{
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@ -171,11 +226,3 @@ void plat_gic_setup(void)
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if (sizeof(tegra186_sec_irqs) > 0)
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if (sizeof(tegra186_sec_irqs) > 0)
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tegra_fiq_handler_setup();
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tegra_fiq_handler_setup();
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}
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}
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/*******************************************************************************
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* Handler for early platform setup
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******************************************************************************/
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void plat_early_platform_setup(void)
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{
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mce_verify_firmware_version();
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}
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