From 1f1c0206d8513e07a64b84b374b461c3db61b49c Mon Sep 17 00:00:00 2001 From: "Abdul Halim, Muhammad Hadi Asyrafi" Date: Mon, 29 Jun 2020 12:15:27 +0800 Subject: [PATCH] build(intel): define a macro for SIMICS build SIMICS builds have different UART configurations compared to hardware build. Hence, this patch defines a macro to differentiate between both. Signed-off-by: Abdul Halim, Muhammad Hadi Asyrafi Signed-off-by: Sieu Mun Tang Change-Id: Iadecd5445e06611486ac3c6a214a6d0dc8ccd27b --- Makefile | 5 +++++ plat/intel/soc/agilex/platform.mk | 5 +++-- plat/intel/soc/common/include/platform_def.h | 7 +++++++ plat/intel/soc/n5x/platform.mk | 1 + plat/intel/soc/stratix10/platform.mk | 5 +++-- 5 files changed, 19 insertions(+), 4 deletions(-) diff --git a/Makefile b/Makefile index cac3e1297..fb50f0c50 100644 --- a/Makefile +++ b/Makefile @@ -945,6 +945,9 @@ PRINT_MEMORY_MAP ?= ${PRINT_MEMORY_MAP_PATH}/print_memory_map.py # Variables for use with documentation build using Sphinx tool DOCS_PATH ?= docs +# Defination of SIMICS flag +SIMICS_BUILD ?= 0 + ################################################################################ # Include BL specific makefiles ################################################################################ @@ -1055,6 +1058,7 @@ $(eval $(call assert_booleans,\ ENABLE_FEAT_FGT \ ENABLE_FEAT_AMUv1 \ ENABLE_FEAT_ECV \ + SIMICS_BUILD \ ))) $(eval $(call assert_numerics,\ @@ -1172,6 +1176,7 @@ $(eval $(call add_defines,\ ENABLE_FEAT_FGT \ ENABLE_FEAT_AMUv1 \ ENABLE_FEAT_ECV \ + SIMICS_BUILD \ ))) ifeq (${SANITIZE_UB},trap) diff --git a/plat/intel/soc/agilex/platform.mk b/plat/intel/soc/agilex/platform.mk index f7554c6ba..92b77545d 100644 --- a/plat/intel/soc/agilex/platform.mk +++ b/plat/intel/soc/agilex/platform.mk @@ -1,6 +1,6 @@ # -# Copyright (c) 2019-2020, ARM Limited and Contributors. All rights reserved. -# Copyright (c) 2019-2020, Intel Corporation. All rights reserved. +# Copyright (c) 2019-2022, ARM Limited and Contributors. All rights reserved. +# Copyright (c) 2019-2022, Intel Corporation. All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause # @@ -73,4 +73,5 @@ PROGRAMMABLE_RESET_ADDRESS := 0 BL2_AT_EL3 := 1 BL2_INV_DCACHE := 0 MULTI_CONSOLE_API := 1 +SIMICS_BUILD := 0 USE_COHERENT_MEM := 1 diff --git a/plat/intel/soc/common/include/platform_def.h b/plat/intel/soc/common/include/platform_def.h index 91417c355..785949391 100644 --- a/plat/intel/soc/common/include/platform_def.h +++ b/plat/intel/soc/common/include/platform_def.h @@ -169,9 +169,16 @@ #define CRASH_CONSOLE_BASE PLAT_UART0_BASE +#ifndef SIMICS_BUILD #define PLAT_BAUDRATE (115200) #define PLAT_UART_CLOCK (100000000) +#else +#define PLAT_BAUDRATE (4800) +#define PLAT_UART_CLOCK (76800) + +#endif + /******************************************************************************* * PHY related constants ******************************************************************************/ diff --git a/plat/intel/soc/n5x/platform.mk b/plat/intel/soc/n5x/platform.mk index f13984840..722694d43 100644 --- a/plat/intel/soc/n5x/platform.mk +++ b/plat/intel/soc/n5x/platform.mk @@ -46,4 +46,5 @@ PROGRAMMABLE_RESET_ADDRESS := 0 BL2_AT_EL3 := 1 BL2_INV_DCACHE := 0 MULTI_CONSOLE_API := 1 +SIMICS_BUILD := 0 USE_COHERENT_MEM := 1 diff --git a/plat/intel/soc/stratix10/platform.mk b/plat/intel/soc/stratix10/platform.mk index d05d2ad30..b47ac9d72 100644 --- a/plat/intel/soc/stratix10/platform.mk +++ b/plat/intel/soc/stratix10/platform.mk @@ -1,6 +1,6 @@ # -# Copyright (c) 2019-2020, ARM Limited and Contributors. All rights reserved. -# Copyright (c) 2019-2020, Intel Corporation. All rights reserved. +# Copyright (c) 2019-2022, ARM Limited and Contributors. All rights reserved. +# Copyright (c) 2019-2022, Intel Corporation. All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause # @@ -69,4 +69,5 @@ BL31_SOURCES += \ PROGRAMMABLE_RESET_ADDRESS := 0 BL2_AT_EL3 := 1 +SIMICS_BUILD := 0 USE_COHERENT_MEM := 1