rcar_gen3: drivers: ddr: Update DDR setting for H3, M3, M3N
[IPL/DDR] - Update H3, M3, M3N DDR setting rev.0.39. Signed-off-by: Chiaki Fujii <chiaki.fujii.wj@renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> # upstream update Change-Id: I0dbf8091f9de9bb6d2d4f94007a5813fff14789f
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@ -510,6 +510,14 @@ static void send_dbcmd(uint32_t cmd)
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dsb_sev();
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dsb_sev();
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}
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}
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static void dbwait_loop(uint32_t wait_loop)
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{
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uint32_t i;
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for (i = 0; i < wait_loop; i++)
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wait_dbcmd();
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}
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/* DDRPHY register access (raw) */
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/* DDRPHY register access (raw) */
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static uint32_t reg_ddrphy_read(uint32_t phyno, uint32_t regadd)
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static uint32_t reg_ddrphy_read(uint32_t phyno, uint32_t regadd)
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{
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{
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@ -866,6 +874,7 @@ struct _jedec_spec1 {
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uint8_t WL;
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uint8_t WL;
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uint8_t nwr;
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uint8_t nwr;
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uint8_t nrtp;
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uint8_t nrtp;
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uint8_t odtlon;
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uint8_t MR1;
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uint8_t MR1;
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uint8_t MR2;
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uint8_t MR2;
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};
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};
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@ -877,21 +886,21 @@ struct _jedec_spec1 {
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#define JS1_MR2(f) (0x00 | ((f) << 3) | (f))
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#define JS1_MR2(f) (0x00 | ((f) << 3) | (f))
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const struct _jedec_spec1 js1[JS1_FREQ_TBL_NUM] = {
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const struct _jedec_spec1 js1[JS1_FREQ_TBL_NUM] = {
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/* 533.333Mbps */
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/* 533.333Mbps */
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{ 800, 6, 6, 4, 6, 8, JS1_MR1(0), JS1_MR2(0) | 0x40 },
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{ 800, 6, 6, 4, 6, 8, 0, JS1_MR1(0), JS1_MR2(0) | 0x40 },
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/* 1066.666Mbps */
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/* 1066.666Mbps */
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{ 1600, 10, 12, 8, 10, 8, JS1_MR1(1), JS1_MR2(1) | 0x40 },
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{ 1600, 10, 12, 8, 10, 8, 0, JS1_MR1(1), JS1_MR2(1) | 0x40 },
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/* 1600.000Mbps */
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/* 1600.000Mbps */
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{ 2400, 14, 16, 12, 16, 8, JS1_MR1(2), JS1_MR2(2) | 0x40 },
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{ 2400, 14, 16, 12, 16, 8, 6, JS1_MR1(2), JS1_MR2(2) | 0x40 },
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/* 2133.333Mbps */
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/* 2133.333Mbps */
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{ 3200, 20, 22, 10, 20, 8, JS1_MR1(3), JS1_MR2(3) },
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{ 3200, 20, 22, 10, 20, 8, 4, JS1_MR1(3), JS1_MR2(3) },
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/* 2666.666Mbps */
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/* 2666.666Mbps */
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{ 4000, 24, 28, 12, 24, 10, JS1_MR1(4), JS1_MR2(4) },
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{ 4000, 24, 28, 12, 24, 10, 4, JS1_MR1(4), JS1_MR2(4) },
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/* 3200.000Mbps */
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/* 3200.000Mbps */
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{ 4800, 28, 32, 14, 30, 12, JS1_MR1(5), JS1_MR2(5) },
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{ 4800, 28, 32, 14, 30, 12, 6, JS1_MR1(5), JS1_MR2(5) },
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/* 3733.333Mbps */
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/* 3733.333Mbps */
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{ 5600, 32, 36, 16, 34, 14, JS1_MR1(6), JS1_MR2(6) },
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{ 5600, 32, 36, 16, 34, 14, 6, JS1_MR1(6), JS1_MR2(6) },
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/* 4266.666Mbps */
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/* 4266.666Mbps */
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{ 6400, 36, 40, 18, 40, 16, JS1_MR1(7), JS1_MR2(7) }
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{ 6400, 36, 40, 18, 40, 16, 8, JS1_MR1(7), JS1_MR2(7) }
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};
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};
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struct _jedec_spec2 {
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struct _jedec_spec2 {
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@ -921,7 +930,8 @@ struct _jedec_spec2 {
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#define js2_tzqcalns 19
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#define js2_tzqcalns 19
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#define js2_tzqlat 20
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#define js2_tzqlat 20
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#define js2_tiedly 21
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#define js2_tiedly 21
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#define JS2_TBLCNT 22
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#define js2_tODTon_min 22
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#define JS2_TBLCNT 23
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#define js2_trcpb (JS2_TBLCNT)
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#define js2_trcpb (JS2_TBLCNT)
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#define js2_trcab (JS2_TBLCNT + 1)
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#define js2_trcab (JS2_TBLCNT + 1)
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@ -954,7 +964,8 @@ const struct _jedec_spec2 jedec_spec2[2][JS2_TBLCNT] = {
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/*tMRD*/ {14000, 10},
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/*tMRD*/ {14000, 10},
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/*tZQCALns*/ {1000 * 10, 0},
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/*tZQCALns*/ {1000 * 10, 0},
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/*tZQLAT*/ {30000, 10},
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/*tZQLAT*/ {30000, 10},
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/*tIEdly*/ {12500, 0}
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/*tIEdly*/ {12500, 0},
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/*tODTon_min*/ {1500, 0}
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}, {
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}, {
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/*tSR */ {15000, 3},
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/*tSR */ {15000, 3},
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/*tXP */ {7500, 3},
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/*tXP */ {7500, 3},
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@ -977,7 +988,8 @@ const struct _jedec_spec2 jedec_spec2[2][JS2_TBLCNT] = {
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/*tMRD*/ {14000, 10},
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/*tMRD*/ {14000, 10},
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/*tZQCALns*/ {1000 * 10, 0},
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/*tZQCALns*/ {1000 * 10, 0},
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/*tZQLAT*/ {30000, 10},
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/*tZQLAT*/ {30000, 10},
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/*tIEdly*/ {12500, 0}
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/*tIEdly*/ {12500, 0},
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/*tODTon_min*/ {1500, 0}
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}
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}
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};
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};
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@ -1452,7 +1464,7 @@ static void ddrtbl_load(void)
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if ((prr_product == PRR_PRODUCT_M3N) ||
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if ((prr_product == PRR_PRODUCT_M3N) ||
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(prr_product == PRR_PRODUCT_V3H)) {
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(prr_product == PRR_PRODUCT_V3H)) {
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ddrtbl_setval(_cnf_DDR_PHY_SLICE_REGSET,
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ddrtbl_setval(_cnf_DDR_PHY_SLICE_REGSET,
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_reg_PHY_RDDATA_EN_OE_DLY, dataS);
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_reg_PHY_RDDATA_EN_OE_DLY, dataS - 2);
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}
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}
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ddrtbl_setval(_cnf_DDR_PI_REGSET, _reg_PI_RDLAT_ADJ_F1, RL - dataS);
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ddrtbl_setval(_cnf_DDR_PI_REGSET, _reg_PI_RDLAT_ADJ_F1, RL - dataS);
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@ -1501,6 +1513,7 @@ static void ddrtbl_load(void)
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/* non */
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/* non */
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} else {
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} else {
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regif_pll_wa();
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regif_pll_wa();
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dbwait_loop(5);
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}
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}
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/* FREQ_SEL_MULTICAST & PER_CS_TRAINING_MULTICAST SET (for safety) */
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/* FREQ_SEL_MULTICAST & PER_CS_TRAINING_MULTICAST SET (for safety) */
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@ -2067,12 +2080,18 @@ static void dbsc_regset(void)
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/* DBTR9.TRDPR : tRTP */
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/* DBTR9.TRDPR : tRTP */
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mmio_write_32(DBSC_DBTR(9), js2[js2_trtp]);
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mmio_write_32(DBSC_DBTR(9), js2[js2_trtp]);
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/* DBTR10.TWR : nwr */
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/* DBTR10.TWR : nWR + 1 */
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mmio_write_32(DBSC_DBTR(10), js1[js1_ind].nwr);
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mmio_write_32(DBSC_DBTR(10), js1[js1_ind].nwr + 1);
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/* DBTR11.TRDWR : RL + tDQSCK + BL/2 + Rounddown(tRPST) - WL + tWPRE */
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/*
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* DBTR11.TRDWR : RL + BL / 2 + Rounddown(tRPST) + PHY_ODTLoff -
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* odtlon + tDQSCK - tODTon,min +
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* PCB delay (out+in) + tPHY_ODToff
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*/
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mmio_write_32(DBSC_DBTR(11),
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mmio_write_32(DBSC_DBTR(11),
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RL + js2[js2_tdqsck] + (16 / 2) + 1 - WL + 2 + 2);
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RL + (16 / 2) + 1 + 2 - js1[js1_ind].odtlon +
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js2[js2_tdqsck] - js2[js2_tODTon_min] +
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_f_scale(ddr_mbps, ddr_mbpsdiv, 1300, 0));
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/* DBTR12.TWRRD : WL + 1 + BL/2 + tWTR */
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/* DBTR12.TWRRD : WL + 1 + BL/2 + tWTR */
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data_l = WL + 1 + (16 / 2) + js2[js2_twtr];
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data_l = WL + 1 + (16 / 2) + js2[js2_twtr];
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@ -2338,10 +2357,23 @@ static void dbsc_regset_post(void)
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}
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}
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}
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}
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if ((prr_product == PRR_PRODUCT_H3) && (prr_cut > PRR_PRODUCT_11)) {
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if ((prr_product == PRR_PRODUCT_H3) && (prr_cut > PRR_PRODUCT_11)) {
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#if RCAR_DRAM_SPLIT == 2
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if (board_cnf->phyvalid == 0x05) {
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mmio_write_32(DBSC_DBTR(24),
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(rdlat_max << 24) + (rdlat_min << 16) +
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mmio_read_32(DBSC_DBTR(24)));
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} else {
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mmio_write_32(DBSC_DBTR(24),
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mmio_write_32(DBSC_DBTR(24),
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((rdlat_max * 2 - rdlat_min + 4) << 24) +
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((rdlat_max * 2 - rdlat_min + 4) << 24) +
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((rdlat_min + 2) << 16) +
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((rdlat_min + 2) << 16) +
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mmio_read_32(DBSC_DBTR(24)));
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mmio_read_32(DBSC_DBTR(24)));
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}
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#else /*RCAR_DRAM_SPLIT == 2 */
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mmio_write_32(DBSC_DBTR(24),
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((rdlat_max * 2 - rdlat_min + 4) << 24) +
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((rdlat_min + 2) << 16) +
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mmio_read_32(DBSC_DBTR(24)));
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#endif /*RCAR_DRAM_SPLIT == 2 */
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} else {
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} else {
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mmio_write_32(DBSC_DBTR(24),
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mmio_write_32(DBSC_DBTR(24),
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((rdlat_max + 2) << 24) +
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((rdlat_max + 2) << 24) +
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@ -3474,10 +3506,13 @@ static uint32_t wdqdm_man(void)
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{
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{
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uint32_t err, retry_cnt;
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uint32_t err, retry_cnt;
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const uint32_t retry_max = 0x10;
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const uint32_t retry_max = 0x10;
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uint32_t ch, ddr_csn, mr14_bkup[4][4];
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uint32_t datal, ch, ddr_csn, mr14_bkup[4][4];
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datal = RL + js2[js2_tdqsck] + (16 / 2) + 1 - WL + 2 + 2 + 19;
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if ((mmio_read_32(DBSC_DBTR(11)) & 0xFF) > datal)
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datal = mmio_read_32(DBSC_DBTR(11)) & 0xFF;
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ddr_setval_ach(_reg_PI_TDFI_WDQLVL_RW, datal);
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ddr_setval_ach(_reg_PI_TDFI_WDQLVL_RW,
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(mmio_read_32(DBSC_DBTR(11)) & 0xFF) + 19);
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if (((prr_product == PRR_PRODUCT_H3) && (prr_cut > PRR_PRODUCT_11)) ||
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if (((prr_product == PRR_PRODUCT_H3) && (prr_cut > PRR_PRODUCT_11)) ||
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(prr_product == PRR_PRODUCT_M3N) ||
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(prr_product == PRR_PRODUCT_M3N) ||
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(prr_product == PRR_PRODUCT_V3H)) {
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(prr_product == PRR_PRODUCT_V3H)) {
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@ -1727,8 +1727,13 @@ static uint32_t _board_judge(void)
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#endif
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#endif
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}
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}
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} else if (prr_product == PRR_PRODUCT_M3) {
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} else if (prr_product == PRR_PRODUCT_M3) {
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if (prr_cut >= PRR_PRODUCT_30) {
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/* RENESAS Starter Kit (M3-W Ver.3.0/SIP) */
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brd = 18;
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} else {
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/* RENESAS Starter Kit(M3-W/SIP 8Gbit 1rank) board */
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/* RENESAS Starter Kit(M3-W/SIP 8Gbit 1rank) board */
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brd = 3;
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brd = 3;
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}
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} else {
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} else {
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/* RENESAS Starter Kit(M3-N/SIP) board */
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/* RENESAS Starter Kit(M3-N/SIP) board */
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brd = 11;
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brd = 11;
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@ -5,7 +5,7 @@
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* SPDX-License-Identifier: BSD-3-Clause
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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*/
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#define RCAR_DDR_VERSION "rev.0.38"
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#define RCAR_DDR_VERSION "rev.0.39"
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#define DRAM_CH_CNT 0x04
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#define DRAM_CH_CNT 0x04
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#define SLICE_CNT 0x04
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#define SLICE_CNT 0x04
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#define CS_CNT 0x02
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#define CS_CNT 0x02
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@ -1,5 +1,5 @@
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/*
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/*
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* Copyright (c) 2015-2019, Renesas Electronics Corporation.
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* Copyright (c) 2015-2020, Renesas Electronics Corporation.
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* All rights reserved.
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* All rights reserved.
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*
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*
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* SPDX-License-Identifier: BSD-3-Clause
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* SPDX-License-Identifier: BSD-3-Clause
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@ -116,7 +116,7 @@ static const uint32_t DDR_PHY_SLICE_REGSET_M3N[DDR_PHY_SLICE_REGSET_NUM_M3N] = {
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/*0859*/ 0x00000200,
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/*0859*/ 0x00000200,
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/*085a*/ 0x00000004,
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/*085a*/ 0x00000004,
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/*085b*/ 0x4041a151,
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/*085b*/ 0x4041a151,
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/*085c*/ 0x0141c0a0,
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/*085c*/ 0x0141a0a0,
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/*085d*/ 0x0000c0c0,
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/*085d*/ 0x0000c0c0,
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/*085e*/ 0x0e0c000e,
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/*085e*/ 0x0e0c000e,
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/*085f*/ 0x10001000,
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/*085f*/ 0x10001000,
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