rcar_gen3: drivers: qos: M3W: Use common register definition
Use common qos_regs.h instead of a local copy in the M3W QoS init. Fill missing registers into qos_regs.h . No functional change. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Change-Id: I91175c86cdb94b9271c880df2cb65949f15f1bad
This commit is contained in:
Marek Vasut
parent
fbcdc4ebe7
commit
1f49a943e2
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2015-2017, Renesas Electronics Corporation. All rights reserved.
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* Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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@ -9,131 +9,11 @@
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#include <common/debug.h>
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#include "../qos_common.h"
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#include "../qos_reg.h"
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#include "qos_init_m3_v10.h"
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#define RCAR_QOS_VERSION "rev.0.19"
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#define RCAR_QOS_NONE (3U)
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#define RCAR_QOS_TYPE_DEFAULT (0U)
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#define RCAR_DRAM_SPLIT_LINEAR (0U)
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#define RCAR_DRAM_SPLIT_4CH (1U)
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#define RCAR_DRAM_SPLIT_2CH (2U)
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#define RCAR_DRAM_SPLIT_AUTO (3U)
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#define RST_BASE (0xE6160000U)
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#define RST_MODEMR (RST_BASE + 0x0060U)
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#define DBSC_BASE (0xE6790000U)
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#define DBSC_DBCAM0CNF0 (DBSC_BASE + 0x0900U)
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#define DBSC_DBCAM0CNF1 (DBSC_BASE + 0x0904U)
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#define DBSC_DBCAM0CNF2 (DBSC_BASE + 0x0908U)
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#define DBSC_DBCAM0CNF3 (DBSC_BASE + 0x090CU)
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#define DBSC_DBCAMDIS (DBSC_BASE + 0x09fCU)
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#define DBSC_DBSCHCNT0 (DBSC_BASE + 0x1000U)
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#define DBSC_DBSCHCNT1 (DBSC_BASE + 0x1004U)
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#define DBSC_DBSCHSZ0 (DBSC_BASE + 0x1010U)
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#define DBSC_DBSCHRW0 (DBSC_BASE + 0x1020U)
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#define DBSC_DBSCHQOS_0_0 (DBSC_BASE + 0x1030U)
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#define DBSC_DBSCHQOS_0_1 (DBSC_BASE + 0x1034U)
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#define DBSC_DBSCHQOS_0_2 (DBSC_BASE + 0x1038U)
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#define DBSC_DBSCHQOS_0_3 (DBSC_BASE + 0x103CU)
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#define DBSC_DBSCHQOS_1_0 (DBSC_BASE + 0x1040U)
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#define DBSC_DBSCHQOS_1_1 (DBSC_BASE + 0x1044U)
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#define DBSC_DBSCHQOS_1_2 (DBSC_BASE + 0x1048U)
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#define DBSC_DBSCHQOS_1_3 (DBSC_BASE + 0x104CU)
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#define DBSC_DBSCHQOS_2_0 (DBSC_BASE + 0x1050U)
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#define DBSC_DBSCHQOS_2_1 (DBSC_BASE + 0x1054U)
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#define DBSC_DBSCHQOS_2_2 (DBSC_BASE + 0x1058U)
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#define DBSC_DBSCHQOS_2_3 (DBSC_BASE + 0x105CU)
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#define DBSC_DBSCHQOS_3_0 (DBSC_BASE + 0x1060U)
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#define DBSC_DBSCHQOS_3_1 (DBSC_BASE + 0x1064U)
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#define DBSC_DBSCHQOS_3_2 (DBSC_BASE + 0x1068U)
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#define DBSC_DBSCHQOS_3_3 (DBSC_BASE + 0x106CU)
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#define DBSC_DBSCHQOS_4_0 (DBSC_BASE + 0x1070U)
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#define DBSC_DBSCHQOS_4_1 (DBSC_BASE + 0x1074U)
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#define DBSC_DBSCHQOS_4_2 (DBSC_BASE + 0x1078U)
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#define DBSC_DBSCHQOS_4_3 (DBSC_BASE + 0x107CU)
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#define DBSC_DBSCHQOS_5_0 (DBSC_BASE + 0x1080U)
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#define DBSC_DBSCHQOS_5_1 (DBSC_BASE + 0x1084U)
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#define DBSC_DBSCHQOS_5_2 (DBSC_BASE + 0x1088U)
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#define DBSC_DBSCHQOS_5_3 (DBSC_BASE + 0x108CU)
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#define DBSC_DBSCHQOS_6_0 (DBSC_BASE + 0x1090U)
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#define DBSC_DBSCHQOS_6_1 (DBSC_BASE + 0x1094U)
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#define DBSC_DBSCHQOS_6_2 (DBSC_BASE + 0x1098U)
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#define DBSC_DBSCHQOS_6_3 (DBSC_BASE + 0x109CU)
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#define DBSC_DBSCHQOS_7_0 (DBSC_BASE + 0x10A0U)
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#define DBSC_DBSCHQOS_7_1 (DBSC_BASE + 0x10A4U)
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#define DBSC_DBSCHQOS_7_2 (DBSC_BASE + 0x10A8U)
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#define DBSC_DBSCHQOS_7_3 (DBSC_BASE + 0x10ACU)
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#define DBSC_DBSCHQOS_8_0 (DBSC_BASE + 0x10B0U)
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#define DBSC_DBSCHQOS_8_1 (DBSC_BASE + 0x10B4U)
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#define DBSC_DBSCHQOS_8_2 (DBSC_BASE + 0x10B8U)
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#define DBSC_DBSCHQOS_8_3 (DBSC_BASE + 0x10BCU)
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#define DBSC_DBSCHQOS_9_0 (DBSC_BASE + 0x10C0U)
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#define DBSC_DBSCHQOS_9_1 (DBSC_BASE + 0x10C4U)
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#define DBSC_DBSCHQOS_9_2 (DBSC_BASE + 0x10C8U)
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#define DBSC_DBSCHQOS_9_3 (DBSC_BASE + 0x10CCU)
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#define DBSC_DBSCHQOS_10_0 (DBSC_BASE + 0x10D0U)
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#define DBSC_DBSCHQOS_10_1 (DBSC_BASE + 0x10D4U)
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#define DBSC_DBSCHQOS_10_2 (DBSC_BASE + 0x10D8U)
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#define DBSC_DBSCHQOS_10_3 (DBSC_BASE + 0x10DCU)
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#define DBSC_DBSCHQOS_11_0 (DBSC_BASE + 0x10E0U)
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#define DBSC_DBSCHQOS_11_1 (DBSC_BASE + 0x10E4U)
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#define DBSC_DBSCHQOS_11_2 (DBSC_BASE + 0x10E8U)
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#define DBSC_DBSCHQOS_11_3 (DBSC_BASE + 0x10ECU)
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#define DBSC_DBSCHQOS_12_0 (DBSC_BASE + 0x10F0U)
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#define DBSC_DBSCHQOS_12_1 (DBSC_BASE + 0x10F4U)
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#define DBSC_DBSCHQOS_12_2 (DBSC_BASE + 0x10F8U)
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#define DBSC_DBSCHQOS_12_3 (DBSC_BASE + 0x10FCU)
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#define DBSC_DBSCHQOS_13_0 (DBSC_BASE + 0x1100U)
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#define DBSC_DBSCHQOS_13_1 (DBSC_BASE + 0x1104U)
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#define DBSC_DBSCHQOS_13_2 (DBSC_BASE + 0x1108U)
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#define DBSC_DBSCHQOS_13_3 (DBSC_BASE + 0x110CU)
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#define DBSC_DBSCHQOS_14_0 (DBSC_BASE + 0x1110U)
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#define DBSC_DBSCHQOS_14_1 (DBSC_BASE + 0x1114U)
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#define DBSC_DBSCHQOS_14_2 (DBSC_BASE + 0x1118U)
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#define DBSC_DBSCHQOS_14_3 (DBSC_BASE + 0x111CU)
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#define DBSC_DBSCHQOS_15_0 (DBSC_BASE + 0x1120U)
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#define DBSC_DBSCHQOS_15_1 (DBSC_BASE + 0x1124U)
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#define DBSC_DBSCHQOS_15_2 (DBSC_BASE + 0x1128U)
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#define DBSC_DBSCHQOS_15_3 (DBSC_BASE + 0x112CU)
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#define DBSC_SCFCTST2 (DBSC_BASE + 0x170CU)
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#define AXI_BASE (0xE6784000U)
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#define AXI_ADSPLCR0 (AXI_BASE + 0x0008U)
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#define AXI_ADSPLCR1 (AXI_BASE + 0x000CU)
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#define AXI_ADSPLCR2 (AXI_BASE + 0x0010U)
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#define AXI_ADSPLCR3 (AXI_BASE + 0x0014U)
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#define ADSPLCR0_ADRMODE_DEFAULT ((uint32_t)0U << 31U)
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#define ADSPLCR0_ADRMODE_GEN2 ((uint32_t)1U << 31U)
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#define ADSPLCR0_SPLITSEL(x) ((uint32_t)(x) << 16U)
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#define ADSPLCR0_AREA(x) ((uint32_t)(x) << 8U)
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#define ADSPLCR0_SWP (0x0CU)
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#define MSTAT_BASE (0xE67E0000U)
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#define MSTAT_FIX_QOS_BANK0 (MSTAT_BASE + 0x0000U)
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#define MSTAT_FIX_QOS_BANK1 (MSTAT_BASE + 0x1000U)
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#define MSTAT_BE_QOS_BANK0 (MSTAT_BASE + 0x2000U)
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#define MSTAT_BE_QOS_BANK1 (MSTAT_BASE + 0x3000U)
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#define MSTAT_SL_INIT (MSTAT_BASE + 0x8000U)
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#define MSTAT_REF_ARS (MSTAT_BASE + 0x8004U)
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#define MSTAT_STATQC (MSTAT_BASE + 0x8008U)
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#define RALLOC_BASE (0xE67F0000U)
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#define RALLOC_RAS (RALLOC_BASE + 0x0000U)
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#define RALLOC_FIXTH (RALLOC_BASE + 0x0004U)
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#define RALLOC_RAEN (RALLOC_BASE + 0x0018U)
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#define RALLOC_REGGD (RALLOC_BASE + 0x0020U)
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#define RALLOC_DANN (RALLOC_BASE + 0x0030U)
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#define RALLOC_DANT (RALLOC_BASE + 0x0038U)
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#define RALLOC_EC (RALLOC_BASE + 0x003CU)
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#define RALLOC_EMS (RALLOC_BASE + 0x0040U)
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#define RALLOC_FSS (RALLOC_BASE + 0x0048U)
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#define RALLOC_INSFC (RALLOC_BASE + 0x0050U)
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#define RALLOC_BERR (RALLOC_BASE + 0x0054U)
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#define RALLOC_RACNT0 (RALLOC_BASE + 0x0080U)
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#if RCAR_QOS_TYPE == RCAR_QOS_TYPE_DEFAULT
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static const mstat_slot_t mstat_fix[] = {
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{0x0000U, 0x0000000000000000UL},
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@ -392,70 +272,70 @@ static void dbsc_setting(void)
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}
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/* QoS Settings */
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io_write_32(DBSC_DBSCHQOS_0_0, 0x00000F00);
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io_write_32(DBSC_DBSCHQOS_0_1, 0x00000B00);
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io_write_32(DBSC_DBSCHQOS_0_2, 0x00000000);
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io_write_32(DBSC_DBSCHQOS_0_3, 0x00000000);
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/* DBSC_DBSCHQOS_1_0 not set */
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/* DBSC_DBSCHQOS_1_1 not set */
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/* DBSC_DBSCHQOS_1_2 not set */
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/* DBSC_DBSCHQOS_1_3 not set */
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/* DBSC_DBSCHQOS_2_0 not set */
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/* DBSC_DBSCHQOS_2_1 not set */
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/* DBSC_DBSCHQOS_2_2 not set */
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/* DBSC_DBSCHQOS_2_3 not set */
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/* DBSC_DBSCHQOS_3_0 not set */
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/* DBSC_DBSCHQOS_3_1 not set */
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/* DBSC_DBSCHQOS_3_2 not set */
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/* DBSC_DBSCHQOS_3_3 not set */
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io_write_32(DBSC_DBSCHQOS_4_0, 0x00000300);
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io_write_32(DBSC_DBSCHQOS_4_1, 0x000002F0);
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io_write_32(DBSC_DBSCHQOS_4_2, 0x00000200);
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io_write_32(DBSC_DBSCHQOS_4_3, 0x00000100);
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/* DBSC_DBSCHQOS_5_0 not set */
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/* DBSC_DBSCHQOS_5_1 not set */
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/* DBSC_DBSCHQOS_5_2 not set */
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/* DBSC_DBSCHQOS_5_3 not set */
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/* DBSC_DBSCHQOS_6_0 not set */
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/* DBSC_DBSCHQOS_6_1 not set */
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/* DBSC_DBSCHQOS_6_2 not set */
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/* DBSC_DBSCHQOS_6_3 not set */
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/* DBSC_DBSCHQOS_7_0 not set */
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/* DBSC_DBSCHQOS_7_1 not set */
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/* DBSC_DBSCHQOS_7_2 not set */
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/* DBSC_DBSCHQOS_7_3 not set */
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/* DBSC_DBSCHQOS_8_0 not set */
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/* DBSC_DBSCHQOS_8_1 not set */
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/* DBSC_DBSCHQOS_8_2 not set */
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/* DBSC_DBSCHQOS_8_3 not set */
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io_write_32(DBSC_DBSCHQOS_9_0, 0x00000300);
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io_write_32(DBSC_DBSCHQOS_9_1, 0x000002F0);
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io_write_32(DBSC_DBSCHQOS_9_2, 0x00000200);
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io_write_32(DBSC_DBSCHQOS_9_3, 0x00000100);
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/* DBSC_DBSCHQOS_10_0 not set */
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/* DBSC_DBSCHQOS_10_1 not set */
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/* DBSC_DBSCHQOS_10_2 not set */
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/* DBSC_DBSCHQOS_10_3 not set */
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/* DBSC_DBSCHQOS_11_0 not set */
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/* DBSC_DBSCHQOS_11_1 not set */
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/* DBSC_DBSCHQOS_11_2 not set */
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/* DBSC_DBSCHQOS_11_3 not set */
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/* DBSC_DBSCHQOS_12_0 not set */
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/* DBSC_DBSCHQOS_12_1 not set */
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/* DBSC_DBSCHQOS_12_2 not set */
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/* DBSC_DBSCHQOS_12_3 not set */
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io_write_32(DBSC_DBSCHQOS_13_0, 0x00000100);
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io_write_32(DBSC_DBSCHQOS_13_1, 0x000000F0);
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io_write_32(DBSC_DBSCHQOS_13_2, 0x000000A0);
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io_write_32(DBSC_DBSCHQOS_13_3, 0x00000040);
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io_write_32(DBSC_DBSCHQOS_14_0, 0x000000C0);
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io_write_32(DBSC_DBSCHQOS_14_1, 0x000000B0);
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io_write_32(DBSC_DBSCHQOS_14_2, 0x00000080);
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io_write_32(DBSC_DBSCHQOS_14_3, 0x00000040);
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io_write_32(DBSC_DBSCHQOS_15_0, 0x00000040);
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io_write_32(DBSC_DBSCHQOS_15_1, 0x00000030);
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io_write_32(DBSC_DBSCHQOS_15_2, 0x00000020);
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io_write_32(DBSC_DBSCHQOS_15_3, 0x00000010);
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io_write_32(DBSC_DBSCHQOS00, 0x00000F00);
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io_write_32(DBSC_DBSCHQOS01, 0x00000B00);
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io_write_32(DBSC_DBSCHQOS02, 0x00000000);
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io_write_32(DBSC_DBSCHQOS03, 0x00000000);
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/* DBSC_DBSCHQOS10 not set */
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/* DBSC_DBSCHQOS11 not set */
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/* DBSC_DBSCHQOS12 not set */
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/* DBSC_DBSCHQOS13 not set */
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/* DBSC_DBSCHQOS20 not set */
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/* DBSC_DBSCHQOS21 not set */
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/* DBSC_DBSCHQOS22 not set */
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/* DBSC_DBSCHQOS23 not set */
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/* DBSC_DBSCHQOS30 not set */
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/* DBSC_DBSCHQOS31 not set */
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/* DBSC_DBSCHQOS32 not set */
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/* DBSC_DBSCHQOS33 not set */
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io_write_32(DBSC_DBSCHQOS40, 0x00000300);
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io_write_32(DBSC_DBSCHQOS41, 0x000002F0);
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io_write_32(DBSC_DBSCHQOS42, 0x00000200);
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io_write_32(DBSC_DBSCHQOS43, 0x00000100);
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/* DBSC_DBSCHQOS50 not set */
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/* DBSC_DBSCHQOS51 not set */
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/* DBSC_DBSCHQOS52 not set */
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/* DBSC_DBSCHQOS53 not set */
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/* DBSC_DBSCHQOS60 not set */
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/* DBSC_DBSCHQOS61 not set */
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/* DBSC_DBSCHQOS62 not set */
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/* DBSC_DBSCHQOS63 not set */
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/* DBSC_DBSCHQOS70 not set */
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/* DBSC_DBSCHQOS71 not set */
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/* DBSC_DBSCHQOS72 not set */
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/* DBSC_DBSCHQOS73 not set */
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/* DBSC_DBSCHQOS80 not set */
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/* DBSC_DBSCHQOS81 not set */
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/* DBSC_DBSCHQOS82 not set */
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/* DBSC_DBSCHQOS83 not set */
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io_write_32(DBSC_DBSCHQOS90, 0x00000300);
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io_write_32(DBSC_DBSCHQOS91, 0x000002F0);
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io_write_32(DBSC_DBSCHQOS92, 0x00000200);
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io_write_32(DBSC_DBSCHQOS93, 0x00000100);
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/* DBSC_DBSCHQOS100 not set */
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/* DBSC_DBSCHQOS101 not set */
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/* DBSC_DBSCHQOS102 not set */
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/* DBSC_DBSCHQOS103 not set */
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/* DBSC_DBSCHQOS110 not set */
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/* DBSC_DBSCHQOS111 not set */
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/* DBSC_DBSCHQOS112 not set */
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/* DBSC_DBSCHQOS113 not set */
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/* DBSC_DBSCHQOS120 not set */
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/* DBSC_DBSCHQOS121 not set */
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/* DBSC_DBSCHQOS122 not set */
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/* DBSC_DBSCHQOS123 not set */
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io_write_32(DBSC_DBSCHQOS130, 0x00000100);
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io_write_32(DBSC_DBSCHQOS131, 0x000000F0);
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io_write_32(DBSC_DBSCHQOS132, 0x000000A0);
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io_write_32(DBSC_DBSCHQOS133, 0x00000040);
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io_write_32(DBSC_DBSCHQOS140, 0x000000C0);
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io_write_32(DBSC_DBSCHQOS141, 0x000000B0);
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io_write_32(DBSC_DBSCHQOS142, 0x00000080);
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io_write_32(DBSC_DBSCHQOS143, 0x00000040);
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io_write_32(DBSC_DBSCHQOS150, 0x00000040);
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io_write_32(DBSC_DBSCHQOS151, 0x00000030);
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io_write_32(DBSC_DBSCHQOS152, 0x00000020);
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io_write_32(DBSC_DBSCHQOS153, 0x00000010);
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}
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void qos_init_m3_v10(void)
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@ -490,37 +370,37 @@ void qos_init_m3_v10(void)
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#endif
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/* Resource Alloc setting */
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io_write_32(RALLOC_RAS, 0x00000028U);
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io_write_32(RALLOC_FIXTH, 0x000F0005U);
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io_write_32(RALLOC_REGGD, 0x00000000U);
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io_write_64(RALLOC_DANN, 0x0101010102020201UL);
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io_write_32(RALLOC_DANT, 0x00100804U);
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io_write_32(RALLOC_EC, 0x00000000U);
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io_write_64(RALLOC_EMS, 0x0000000000000000UL);
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io_write_32(RALLOC_FSS, 0x000003e8U);
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io_write_32(RALLOC_INSFC, 0xC7840001U);
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io_write_32(RALLOC_BERR, 0x00000000U);
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io_write_32(RALLOC_RACNT0, 0x00000000U);
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io_write_32(QOSCTRL_RAS, 0x00000028U);
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io_write_32(QOSCTRL_FIXTH, 0x000F0005U);
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io_write_32(QOSCTRL_REGGD, 0x00000000U);
|
||||
io_write_64(QOSCTRL_DANN, 0x0101010102020201UL);
|
||||
io_write_32(QOSCTRL_DANT, 0x00100804U);
|
||||
io_write_32(QOSCTRL_EC, 0x00000000U);
|
||||
io_write_64(QOSCTRL_EMS, 0x0000000000000000UL);
|
||||
io_write_32(QOSCTRL_FSS, 0x000003e8U);
|
||||
io_write_32(QOSCTRL_INSFC, 0xC7840001U);
|
||||
io_write_32(QOSCTRL_BERR, 0x00000000U);
|
||||
io_write_32(QOSCTRL_RACNT0, 0x00000000U);
|
||||
|
||||
/* MSTAT setting */
|
||||
io_write_32(MSTAT_SL_INIT,
|
||||
/* QOSBW setting */
|
||||
io_write_32(QOSCTRL_SL_INIT,
|
||||
SL_INIT_REFFSSLOT | SL_INIT_SLOTSSLOT | SL_INIT_SSLOTCLK);
|
||||
io_write_32(MSTAT_REF_ARS, 0x00330000U);
|
||||
io_write_32(QOSCTRL_REF_ARS, 0x00330000U);
|
||||
|
||||
/* MSTAT SRAM setting */
|
||||
/* QOSBW SRAM setting */
|
||||
{
|
||||
uint32_t i;
|
||||
|
||||
for (i = 0U; i < ARRAY_SIZE(mstat_fix); i++) {
|
||||
io_write_64(MSTAT_FIX_QOS_BANK0 + mstat_fix[i].addr,
|
||||
io_write_64(QOSBW_FIX_QOS_BANK0 + mstat_fix[i].addr,
|
||||
mstat_fix[i].value);
|
||||
io_write_64(MSTAT_FIX_QOS_BANK1 + mstat_fix[i].addr,
|
||||
io_write_64(QOSBW_FIX_QOS_BANK1 + mstat_fix[i].addr,
|
||||
mstat_fix[i].value);
|
||||
}
|
||||
for (i = 0U; i < ARRAY_SIZE(mstat_be); i++) {
|
||||
io_write_64(MSTAT_BE_QOS_BANK0 + mstat_be[i].addr,
|
||||
io_write_64(QOSBW_BE_QOS_BANK0 + mstat_be[i].addr,
|
||||
mstat_be[i].value);
|
||||
io_write_64(MSTAT_BE_QOS_BANK1 + mstat_be[i].addr,
|
||||
io_write_64(QOSBW_BE_QOS_BANK1 + mstat_be[i].addr,
|
||||
mstat_be[i].value);
|
||||
}
|
||||
}
|
||||
|
|
@ -541,16 +421,16 @@ void qos_init_m3_v10(void)
|
|||
io_write_32(0xFFC51800U, 0x00000000U);
|
||||
|
||||
/* Resource Alloc start */
|
||||
io_write_32(RALLOC_RAEN, 0x00000001U);
|
||||
io_write_32(QOSCTRL_RAEN, 0x00000001U);
|
||||
|
||||
/* MSTAT start */
|
||||
io_write_32(MSTAT_STATQC, 0x00000001U);
|
||||
/* QOSBW start */
|
||||
io_write_32(QOSCTRL_STATQC, 0x00000001U);
|
||||
#else
|
||||
NOTICE("BL2: QoS is None\n");
|
||||
|
||||
/* Resource Alloc setting */
|
||||
io_write_32(RALLOC_EC, 0x00000000U);
|
||||
io_write_32(QOSCTRL_EC, 0x00000000U);
|
||||
/* Resource Alloc start */
|
||||
io_write_32(RALLOC_RAEN, 0x00000001U);
|
||||
io_write_32(QOSCTRL_RAEN, 0x00000001U);
|
||||
#endif /* !(RCAR_QOS_TYPE == RCAR_QOS_NONE) */
|
||||
}
|
||||
|
|
|
|||
|
|
@ -14,7 +14,6 @@
|
|||
|
||||
#define RCAR_QOS_VERSION "rev.0.19"
|
||||
|
||||
|
||||
#define QOSWT_TIME_BANK0 (20000000U) /* unit:ns */
|
||||
|
||||
#define QOSWT_WTEN_ENABLE (0x1U)
|
||||
|
|
|
|||
|
|
@ -14,9 +14,6 @@
|
|||
|
||||
#define RCAR_QOS_VERSION "rev.0.03"
|
||||
|
||||
#define QOSCTRL_EARLYR (QOS_BASE1 + 0x0060U)
|
||||
#define QOSCTRL_FSS (QOS_BASE1 + 0x0048U)
|
||||
|
||||
#define QOSWT_TIME_BANK0 (20000000U) //unit:ns
|
||||
|
||||
#define QOSWT_WTEN_ENABLE (0x1U)
|
||||
|
|
|
|||
Loading…
Reference in New Issue