Merge "plat: marvell: armada: a3k: improve 4GB DRAM usage from 3.375 GB to 3.75 GB" into integration
This commit is contained in:
Lauren Wehrmeister
TrustedFirmware Code Review
commit
1f64caeac8
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@ -1,5 +1,5 @@
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#
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# Copyright (C) 2018-2020 Marvell International Ltd.
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# Copyright (C) 2018-2021 Marvell International Ltd.
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#
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# SPDX-License-Identifier: BSD-3-Clause
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# https://spdx.org/licenses
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@ -38,7 +38,6 @@ PLAT_INCLUDES := -I$(PLAT_FAMILY_BASE)/$(PLAT) \
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-I$/drivers/arm/gic/common/
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PLAT_BL_COMMON_SOURCES := $(PLAT_COMMON_BASE)/aarch64/a3700_common.c \
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$(MARVELL_COMMON_BASE)/marvell_cci.c \
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$(MARVELL_DRV_BASE)/uart/a3700_console.S
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BL1_SOURCES += $(PLAT_COMMON_BASE)/aarch64/plat_helpers.S \
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@ -50,12 +49,14 @@ MARVELL_DRV := $(MARVELL_DRV_BASE)/comphy/phy-comphy-3700.c
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BL31_SOURCES += lib/cpus/aarch64/cortex_a53.S \
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$(PLAT_COMMON_BASE)/aarch64/plat_helpers.S \
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$(PLAT_COMMON_BASE)/plat_cci.c \
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$(PLAT_COMMON_BASE)/plat_pm.c \
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$(PLAT_COMMON_BASE)/dram_win.c \
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$(PLAT_COMMON_BASE)/io_addr_dec.c \
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$(PLAT_COMMON_BASE)/marvell_plat_config.c \
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$(PLAT_COMMON_BASE)/a3700_ea.c \
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$(PLAT_FAMILY_BASE)/$(PLAT)/plat_bl31_setup.c \
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$(MARVELL_COMMON_BASE)/marvell_cci.c \
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$(MARVELL_COMMON_BASE)/marvell_ddr_info.c \
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$(MARVELL_COMMON_BASE)/marvell_gicv3.c \
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$(MARVELL_GIC_SOURCES) \
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@ -1,5 +1,5 @@
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/*
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* Copyright (C) 2018 Marvell International Ltd.
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* Copyright (C) 2018-2021 Marvell International Ltd.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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* https://spdx.org/licenses
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@ -92,33 +92,35 @@ struct cpu_win_configuration mv_cpu_wins[CPU_WIN_CONFIG_MAX][MV_CPU_WIN_NUM] = {
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},
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/*
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* If total dram size is more than 2GB, now there is only one case - 4GB
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* dram; we will use below cpu windows configurations:
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* - Internal Regs, CCI-400, Boot Rom and PCIe windows are kept as
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* default;
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* - Use 4 CPU decode windows for DRAM, which cover 3.375GB DRAM;
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* DDR window 0 is configured in tim header with 2GB size, no need to
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* configure it again here;
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* If total DRAM size is more than 2GB, now there is only one case:
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* 4GB of DRAM; to better utilize address space (for maximization of
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* DRAM usage), we will use the configuration of CPU windows below:
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* - Internal Regs and Boot ROM windows are kept as default;
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* - CCI-400 is moved from its default address to another address
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* (this is actually done even if DRAM size is not more than 2 GB,
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* because the firmware is compiled with that address as a
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* constant);
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* - PCIe window is moved to another address;
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* - Use 4 CPU decode windows for DRAM, which cover 3.75GB DRAM;
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* DDR window 0 is configured in tim header with 2G B size, no need
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* to configure it again here;
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*
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* 0xFFFFFFFF ---> |-----------------------|
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* | Boot ROM | 64KB
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* 0xFFFFFFFF ---> +-----------------------+
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* | Boot ROM | 64 KB
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* 0xFFF00000 ---> +-----------------------+
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* : :
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* 0xF0000000 ---> |-----------------------|
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* | PCIE | 128 MB
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* 0xE8000000 ---> |-----------------------|
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* | DDR window 3 | 128 MB
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* 0xE0000000 ---> +-----------------------+
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* : :
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* 0xD8010000 ---> |-----------------------|
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* | CCI Regs | 64 KB
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* 0xD8000000 ---> +-----------------------+
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* : :
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* 0xFE010000 ---> +-----------------------+
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* | CCI Regs | 64 KB
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* 0xFE000000 ---> +-----------------------+
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* : :
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* 0xFA000000 ---> +-----------------------+
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* | PCIE | 128 MB
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* 0xF2000000 ---> +-----------------------+
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* | DDR window 3 | 512 MB
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* 0xD2000000 ---> +-----------------------+
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* | Internal Regs | 32MB
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* | Internal Regs | 32 MB
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* 0xD0000000 ---> |-----------------------|
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* | DDR window 2 | 256 MB
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* | DDR window 2 | 256 MB
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* 0xC0000000 ---> |-----------------------|
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* | |
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* | DDR window 1 | 1 GB
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@ -155,14 +157,14 @@ struct cpu_win_configuration mv_cpu_wins[CPU_WIN_CONFIG_MAX][MV_CPU_WIN_NUM] = {
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0xc0000000},
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{CPU_WIN_ENABLED,
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CPU_WIN_TARGET_DRAM,
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0xe0000000,
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0x08000000,
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0xe0000000},
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0xd2000000,
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0x20000000,
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0xd2000000},
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{CPU_WIN_ENABLED,
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CPU_WIN_TARGET_PCIE,
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0xe8000000,
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0xf2000000,
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0x08000000,
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0xe8000000},
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0xf2000000},
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},
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};
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@ -1,5 +1,5 @@
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/*
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* Copyright (C) 2018-2020 Marvell International Ltd.
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* Copyright (C) 2018-2021 Marvell International Ltd.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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* https://spdx.org/licenses
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@ -41,8 +41,14 @@
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#define MVEBU_GICR_BASE 0x1D40000
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#define MVEBU_GICC_BASE 0x1D80000
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/* CCI-400 */
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#define MVEBU_CCI_BASE 0x8000000
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/*
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* CCI-400 base address
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* This address is absolute, not relative to MVEBU_REGS_BASE.
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* This is not the default CCI base address (that would be 0xD8000000).
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* Rather we remap CCI to this address to better utilize the address space.
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* (The remapping is done in plat/marvell/armada/a3k/common/plat_cci.c)
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*/
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#define MVEBU_CCI_BASE 0xFE000000
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/*****************************************************************************
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* North and south bridge register base
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@ -1,5 +1,5 @@
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/*
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* Copyright (C) 2016-2019 Marvell International Ltd.
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* Copyright (C) 2016-2021 Marvell International Ltd.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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* https://spdx.org/licenses
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@ -148,7 +148,7 @@
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#define PLAT_MARVELL_SHARED_RAM_CACHED 1
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/* CCI related constants */
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#define PLAT_MARVELL_CCI_BASE (MVEBU_REGS_BASE + MVEBU_CCI_BASE)
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#define PLAT_MARVELL_CCI_BASE MVEBU_CCI_BASE
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#define PLAT_MARVELL_CCI_CLUSTER0_SL_IFACE_IX 3
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#define PLAT_MARVELL_CCI_CLUSTER1_SL_IFACE_IX 4
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@ -227,6 +227,8 @@
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#define CPU_DEC_RLR_REMAP_LOW_MASK \
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(0xffff << CPU_DEC_BR_BASE_OFFS)
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#define CPU_DEC_CCI_BASE_REG (MVEBU_CPU_DEC_WIN_REG_BASE + 0xe0)
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/* Securities */
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#define IRQ_SEC_OS_TICK_INT MARVELL_IRQ_SEC_PHY_TIMER
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@ -0,0 +1,35 @@
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/*
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* Copyright (C) 2021 Marek Behun <marek.behun@nic.cz>
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*
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* Based on plat/marvell/armada/common/marvell_cci.c
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*
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* SPDX-License-Identifier: BSD-3-Clause
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* https://spdx.org/licenses
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*/
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#include <drivers/arm/cci.h>
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#include <lib/mmio.h>
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#include <plat_marvell.h>
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static const int cci_map[] = {
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PLAT_MARVELL_CCI_CLUSTER0_SL_IFACE_IX,
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PLAT_MARVELL_CCI_CLUSTER1_SL_IFACE_IX
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};
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/*
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* This redefines the weak definition in
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* plat/marvell/armada/common/marvell_cci.c
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*/
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void plat_marvell_interconnect_init(void)
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{
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/*
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* To better utilize the address space, we remap CCI base address from
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* the default (0xD8000000) to MVEBU_CCI_BASE.
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* This has to be done here, rather than in cpu_wins_init(), because
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* cpu_wins_init() is called later.
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*/
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mmio_write_32(CPU_DEC_CCI_BASE_REG, MVEBU_CCI_BASE >> 20);
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cci_init(PLAT_MARVELL_CCI_BASE, cci_map, ARRAY_SIZE(cci_map));
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}
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