rcar_gen3: drivers: qos: M3W: Drop extra level of nesting
The extra level of nesting is not necessary, drop it. No functional change. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Change-Id: I086ab1f457866f0e2c3ccd67609c0be35631f893
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@ -168,17 +168,15 @@ void qos_init_m3_v10(void)
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io_write_32(QOSCTRL_REF_ARS, 0x00330000U);
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/* QOSBW SRAM setting */
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{
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uint32_t i;
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uint32_t i;
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for (i = 0U; i < ARRAY_SIZE(mstat_fix); i++) {
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io_write_64(QOSBW_FIX_QOS_BANK0 + i * 8, mstat_fix[i]);
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io_write_64(QOSBW_FIX_QOS_BANK1 + i * 8, mstat_fix[i]);
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}
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for (i = 0U; i < ARRAY_SIZE(mstat_be); i++) {
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io_write_64(QOSBW_BE_QOS_BANK0 + i * 8, mstat_be[i]);
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io_write_64(QOSBW_BE_QOS_BANK1 + i * 8, mstat_be[i]);
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}
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for (i = 0U; i < ARRAY_SIZE(mstat_fix); i++) {
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io_write_64(QOSBW_FIX_QOS_BANK0 + i * 8, mstat_fix[i]);
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io_write_64(QOSBW_FIX_QOS_BANK1 + i * 8, mstat_fix[i]);
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}
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for (i = 0U; i < ARRAY_SIZE(mstat_be); i++) {
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io_write_64(QOSBW_BE_QOS_BANK0 + i * 8, mstat_be[i]);
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io_write_64(QOSBW_BE_QOS_BANK1 + i * 8, mstat_be[i]);
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}
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/* 3DG bus Leaf setting */
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@ -175,30 +175,26 @@ void qos_init_m3_v11(void)
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io_write_32(QOSCTRL_REF_ARS, 0x00330000U);
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#endif /* RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE */
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{
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uint32_t i;
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uint32_t i;
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for (i = 0U; i < ARRAY_SIZE(mstat_fix); i++) {
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io_write_64(QOSBW_FIX_QOS_BANK0 + i * 8, mstat_fix[i]);
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io_write_64(QOSBW_FIX_QOS_BANK1 + i * 8, mstat_fix[i]);
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}
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for (i = 0U; i < ARRAY_SIZE(mstat_be); i++) {
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io_write_64(QOSBW_BE_QOS_BANK0 + i * 8, mstat_be[i]);
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io_write_64(QOSBW_BE_QOS_BANK1 + i * 8, mstat_be[i]);
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}
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#if RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE
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for (i = 0U; i < ARRAY_SIZE(qoswt_fix); i++) {
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io_write_64(QOSWT_FIX_WTQOS_BANK0 + i * 8,
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qoswt_fix[i]);
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io_write_64(QOSWT_FIX_WTQOS_BANK1 + i * 8,
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qoswt_fix[i]);
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}
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for (i = 0U; i < ARRAY_SIZE(qoswt_be); i++) {
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io_write_64(QOSWT_BE_WTQOS_BANK0 + i * 8, qoswt_be[i]);
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io_write_64(QOSWT_BE_WTQOS_BANK1 + i * 8, qoswt_be[i]);
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}
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#endif /* RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE */
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for (i = 0U; i < ARRAY_SIZE(mstat_fix); i++) {
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io_write_64(QOSBW_FIX_QOS_BANK0 + i * 8, mstat_fix[i]);
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io_write_64(QOSBW_FIX_QOS_BANK1 + i * 8, mstat_fix[i]);
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}
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for (i = 0U; i < ARRAY_SIZE(mstat_be); i++) {
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io_write_64(QOSBW_BE_QOS_BANK0 + i * 8, mstat_be[i]);
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io_write_64(QOSBW_BE_QOS_BANK1 + i * 8, mstat_be[i]);
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}
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#if RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE
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for (i = 0U; i < ARRAY_SIZE(qoswt_fix); i++) {
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io_write_64(QOSWT_FIX_WTQOS_BANK0 + i * 8, qoswt_fix[i]);
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io_write_64(QOSWT_FIX_WTQOS_BANK1 + i * 8, qoswt_fix[i]);
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}
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for (i = 0U; i < ARRAY_SIZE(qoswt_be); i++) {
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io_write_64(QOSWT_BE_WTQOS_BANK0 + i * 8, qoswt_be[i]);
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io_write_64(QOSWT_BE_WTQOS_BANK1 + i * 8, qoswt_be[i]);
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}
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#endif /* RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE */
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/* 3DG bus Leaf setting */
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io_write_32(GPU_ACT_GRD, 0x00001234U);
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@ -179,36 +179,26 @@ void qos_init_m3_v30(void)
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io_write_32(QOSCTRL_SL_INIT, SL_INIT_REFFSSLOT | SL_INIT_SLOTSSLOT | SL_INIT_SSLOTCLK_M3_30);
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io_write_32(QOSCTRL_REF_ARS, ((QOSCTRL_REF_ARS_ARBSTOPCYCLE_M3_30 << 16)));
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{
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uint32_t i;
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for (i = 0U; i < ARRAY_SIZE(mstat_fix); i++) {
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io_write_64(QOSBW_FIX_QOS_BANK0 + i*8,
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mstat_fix[i]);
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io_write_64(QOSBW_FIX_QOS_BANK1 + i*8,
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mstat_fix[i]);
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io_write_64(QOSBW_FIX_QOS_BANK0 + i * 8, mstat_fix[i]);
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io_write_64(QOSBW_FIX_QOS_BANK1 + i * 8, mstat_fix[i]);
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}
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for (i = 0U; i < ARRAY_SIZE(mstat_be); i++) {
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io_write_64(QOSBW_BE_QOS_BANK0 + i*8,
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mstat_be[i]);
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io_write_64(QOSBW_BE_QOS_BANK1 + i*8,
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mstat_be[i]);
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io_write_64(QOSBW_BE_QOS_BANK0 + i * 8, mstat_be[i]);
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io_write_64(QOSBW_BE_QOS_BANK1 + i * 8, mstat_be[i]);
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}
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#if RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE
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for (i = 0U; i < ARRAY_SIZE(qoswt_fix); i++) {
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io_write_64(QOSWT_FIX_WTQOS_BANK0 + i*8,
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qoswt_fix[i]);
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io_write_64(QOSWT_FIX_WTQOS_BANK1 + i*8,
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qoswt_fix[i]);
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io_write_64(QOSWT_FIX_WTQOS_BANK0 + i * 8, qoswt_fix[i]);
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io_write_64(QOSWT_FIX_WTQOS_BANK1 + i * 8, qoswt_fix[i]);
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}
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for (i = 0U; i < ARRAY_SIZE(qoswt_be); i++) {
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io_write_64(QOSWT_BE_WTQOS_BANK0 + i*8,
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qoswt_be[i]);
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io_write_64(QOSWT_BE_WTQOS_BANK1 + i*8,
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qoswt_be[i]);
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io_write_64(QOSWT_BE_WTQOS_BANK0 + i * 8, qoswt_be[i]);
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io_write_64(QOSWT_BE_WTQOS_BANK1 + i * 8, qoswt_be[i]);
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}
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#endif /* RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE */
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}
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/* RT bus Leaf setting */
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io_write_32(RT_ACT0, 0x00000000U);
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