Merge "errata: workaround for Cortex A77 errata 1791578" into integration
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commit
204fd9913c
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@ -263,6 +263,9 @@ For Cortex-A77, the following errata build flags are defined :
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- ``ERRATA_A77_1946167``: This applies errata 1946167 workaround to Cortex-A77
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- ``ERRATA_A77_1946167``: This applies errata 1946167 workaround to Cortex-A77
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CPU. This needs to be enabled only for revision <= r1p1 of the CPU.
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CPU. This needs to be enabled only for revision <= r1p1 of the CPU.
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- ``ERRATA_A77_1791578``: This applies errata 1791578 workaround to Cortex-A77
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CPU. This needs to be enabled for r0p0, r1p0, and r1p1, it is still open.
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For Cortex-A78, the following errata build flags are defined :
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For Cortex-A78, the following errata build flags are defined :
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- ``ERRATA_A78_1688305``: This applies errata 1688305 workaround to Cortex-A78
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- ``ERRATA_A78_1688305``: This applies errata 1688305 workaround to Cortex-A78
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@ -1,5 +1,5 @@
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/*
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/*
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* Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2018-2021, ARM Limited and Contributors. All rights reserved.
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*
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*
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* SPDX-License-Identifier: BSD-3-Clause
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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*/
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@ -24,6 +24,12 @@
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#define CORTEX_A77_CPUPWRCTLR_EL1 S3_0_C15_C2_7
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#define CORTEX_A77_CPUPWRCTLR_EL1 S3_0_C15_C2_7
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#define CORTEX_A77_CPUPWRCTLR_EL1_CORE_PWRDN_BIT (U(1) << 0)
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#define CORTEX_A77_CPUPWRCTLR_EL1_CORE_PWRDN_BIT (U(1) << 0)
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/*******************************************************************************
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* CPU Auxiliary Control register specific definitions.
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******************************************************************************/
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#define CORTEX_A77_ACTLR2_EL1 S3_0_C15_C1_1
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#define CORTEX_A77_ACTLR2_EL1_BIT_2 (ULL(1) << 2)
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#define CORTEX_A77_CPUPSELR_EL3 S3_6_C15_C8_0
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#define CORTEX_A77_CPUPSELR_EL3 S3_6_C15_C8_0
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#define CORTEX_A77_CPUPCR_EL3 S3_6_C15_C8_1
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#define CORTEX_A77_CPUPCR_EL3 S3_6_C15_C8_1
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#define CORTEX_A77_CPUPOR_EL3 S3_6_C15_C8_2
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#define CORTEX_A77_CPUPOR_EL3 S3_6_C15_C8_2
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@ -166,6 +166,34 @@ func check_errata_1946167
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b cpu_rev_var_ls
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b cpu_rev_var_ls
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endfunc check_errata_1946167
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endfunc check_errata_1946167
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/* --------------------------------------------------
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* Errata Workaround for Cortex A77 Errata #1791578.
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* This applies to revisions r0p0, r1p0, and r1p1 and is still open.
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* x0: variant[4:7] and revision[0:3] of current cpu.
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* Shall clobber: x0-x17
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* --------------------------------------------------
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*/
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func errata_a77_1791578_wa
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/* Check workaround compatibility. */
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mov x17, x30
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bl check_errata_1791578
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cbz x0, 1f
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/* Set bit 2 in ACTLR2_EL1 */
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mrs x1, CORTEX_A77_ACTLR2_EL1
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orr x1, x1, #CORTEX_A77_ACTLR2_EL1_BIT_2
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msr CORTEX_A77_ACTLR2_EL1, x1
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isb
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1:
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ret x17
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endfunc errata_a77_1791578_wa
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func check_errata_1791578
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/* Applies to r0p0, r1p0, and r1p1 right now */
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mov x1, #0x11
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b cpu_rev_var_ls
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endfunc check_errata_1791578
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/* -------------------------------------------------
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/* -------------------------------------------------
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* The CPU Ops reset function for Cortex-A77.
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* The CPU Ops reset function for Cortex-A77.
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* Shall clobber: x0-x19
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* Shall clobber: x0-x19
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@ -191,6 +219,11 @@ func cortex_a77_reset_func
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bl errata_a77_1946167_wa
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bl errata_a77_1946167_wa
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#endif
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#endif
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#if ERRATA_A77_1791578
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mov x0, x18
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bl errata_a77_1791578_wa
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#endif
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ret x19
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ret x19
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endfunc cortex_a77_reset_func
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endfunc cortex_a77_reset_func
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@ -227,6 +260,7 @@ func cortex_a77_errata_report
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report_errata ERRATA_A77_1508412, cortex_a77, 1508412
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report_errata ERRATA_A77_1508412, cortex_a77, 1508412
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report_errata ERRATA_A77_1925769, cortex_a77, 1925769
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report_errata ERRATA_A77_1925769, cortex_a77, 1925769
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report_errata ERRATA_A77_1946167, cortex_a77, 1946167
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report_errata ERRATA_A77_1946167, cortex_a77, 1946167
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report_errata ERRATA_A77_1791578, cortex_a77, 1791578
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ldp x8, x30, [sp], #16
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ldp x8, x30, [sp], #16
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ret
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ret
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@ -294,6 +294,10 @@ ERRATA_A77_1925769 ?=0
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# only to revision <= r1p1 of the Cortex A77 cpu.
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# only to revision <= r1p1 of the Cortex A77 cpu.
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ERRATA_A77_1946167 ?=0
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ERRATA_A77_1946167 ?=0
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# Flag to apply erratum 1791578 workaround during reset. This erratum applies
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# to revisions r0p0, r1p0, and r1p1, it is still open.
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ERRATA_A77_1791578 ?=0
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# Flag to apply erratum 1688305 workaround during reset. This erratum applies
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# Flag to apply erratum 1688305 workaround during reset. This erratum applies
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# to revisions r0p0 - r1p0 of the A78 cpu.
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# to revisions r0p0 - r1p0 of the A78 cpu.
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ERRATA_A78_1688305 ?=0
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ERRATA_A78_1688305 ?=0
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@ -597,6 +601,10 @@ $(eval $(call add_define,ERRATA_A77_1925769))
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$(eval $(call assert_boolean,ERRATA_A77_1946167))
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$(eval $(call assert_boolean,ERRATA_A77_1946167))
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$(eval $(call add_define,ERRATA_A77_1946167))
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$(eval $(call add_define,ERRATA_A77_1946167))
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# Process ERRATA_A77_1791578 flag
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$(eval $(call assert_boolean,ERRATA_A77_1791578))
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$(eval $(call add_define,ERRATA_A77_1791578))
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# Process ERRATA_A78_1688305 flag
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# Process ERRATA_A78_1688305 flag
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$(eval $(call assert_boolean,ERRATA_A78_1688305))
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$(eval $(call assert_boolean,ERRATA_A78_1688305))
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$(eval $(call add_define,ERRATA_A78_1688305))
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$(eval $(call add_define,ERRATA_A78_1688305))
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