From 20fdf0b05c950c46688ff6d6ee8dd1e1c99d88d6 Mon Sep 17 00:00:00 2001 From: Rajan Vaja Date: Fri, 5 Oct 2018 11:18:42 -0700 Subject: [PATCH] zynqmp: pm: Remove CLK_TOPSW_LSBUS from invalid clock list CLK_TOPSW_LSBUS is parent of WDT clock. Clock from invalid clock list would not be registered to CCF framework and so cannot be used as parent of other clocks. WDT clock has default parent as CLK_TOPSW_LSBUS(APB clock). If CLK_TOPSW_LSBUS is not registered, CCF would not recognize that clock and hence rate of WDT clock would be calculated to be 0 by CCF(as parent rate is considered 0). So it is necessary to allow registration of CLK_TOPSW_LSBUS clock. Signed-off-by: Rajan Vaja Signed-off-by: Jolly Shah Change-Id: Iceaba0f137784fc5fd666e66ffc4c143381c6ccc --- plat/xilinx/zynqmp/pm_service/pm_api_clock.c | 1 - 1 file changed, 1 deletion(-) diff --git a/plat/xilinx/zynqmp/pm_service/pm_api_clock.c b/plat/xilinx/zynqmp/pm_service/pm_api_clock.c index e3050724d..9ea8cd43e 100644 --- a/plat/xilinx/zynqmp/pm_service/pm_api_clock.c +++ b/plat/xilinx/zynqmp/pm_service/pm_api_clock.c @@ -2352,7 +2352,6 @@ static uint32_t pm_clk_invalid_list[] = {CLK_USB0, CLK_USB1, CLK_CSU_SPB, CLK_DBG_TSTMP, CLK_DDR_REF, CLK_TOPSW_MAIN, - CLK_TOPSW_LSBUS, CLK_GTGREF0_REF, CLK_LPD_SWITCH, CLK_CPU_R5,