plat/arm: add board support for rd-daniel platform
Add the initial board support for RD-Daniel Config-M platform. Change-Id: I36df16c745bfe4bc817e275ad4722e5de57733cd Signed-off-by: Jagadeesh Ujja <jagadeesh.ujja@arm.com> Signed-off-by: Aditya Angadi <aditya.angadi@arm.com>
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/*
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* Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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/dts-v1/;
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/ {
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/* compatible string */
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compatible = "arm,rd-daniel";
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/*
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* Place holder for system-id node with default values. The
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* value of platform-id and config-id will be set to the
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* correct values during the BL2 stage of boot.
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*/
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system-id {
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platform-id = <0x0>;
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config-id = <0x0>;
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multi-chip-mode = <0x0>;
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};
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};
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/*
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* Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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/dts-v1/;
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/ {
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/* Platform Config */
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compatible = "arm,tb_fw";
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nt_fw_config_addr = <0x0 0xFEF00000>;
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nt_fw_config_max_size = <0x0100000>;
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/*
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* The following two entries are placeholders for Mbed TLS
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* heap information. The default values don't matter since
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* they will be overwritten by BL1.
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* In case of having shared Mbed TLS heap between BL1 and BL2,
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* BL1 will populate these two properties with the respective
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* info about the shared heap. This info will be available for
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* BL2 in order to locate and re-use the heap.
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*/
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mbedtls_heap_addr = <0x0 0x0>;
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mbedtls_heap_size = <0x0>;
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};
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/*
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* Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef PLATFORM_DEF_H
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#define PLATFORM_DEF_H
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#include <lib/utils_def.h>
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#include <sgi_base_platform_def.h>
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#define PLAT_ARM_CLUSTER_COUNT U(16)
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#define CSS_SGI_MAX_CPUS_PER_CLUSTER U(1)
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#define CSS_SGI_MAX_PE_PER_CPU U(1)
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#define PLAT_CSS_MHU_BASE UL(0x45400000)
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#define PLAT_MHUV2_BASE PLAT_CSS_MHU_BASE
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#define CSS_SYSTEM_PWR_DMN_LVL ARM_PWR_LVL2
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#define PLAT_MAX_PWR_LVL ARM_PWR_LVL1
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/*
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* Physical and virtual address space limits for MMU in AARCH64 & AARCH32 modes
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*/
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#ifdef __aarch64__
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#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 42)
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#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 42)
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#else
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#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32)
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#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32)
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#endif
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/* GIC related constants */
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#define PLAT_ARM_GICD_BASE UL(0x30000000)
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#define PLAT_ARM_GICC_BASE UL(0x2C000000)
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#define PLAT_ARM_GICR_BASE UL(0x30140000)
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#endif /* PLATFORM_DEF_H */
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# Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
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#
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# SPDX-License-Identifier: BSD-3-Clause
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#
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include plat/arm/css/sgi/sgi-common.mk
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RDDANIEL_BASE = plat/arm/board/rddaniel
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PLAT_INCLUDES += -I${RDDANIEL_BASE}/include/
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SGI_CPU_SOURCES := lib/cpus/aarch64/neoverse_zeus.S
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BL1_SOURCES += ${SGI_CPU_SOURCES} \
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${RDDANIEL_BASE}/rddaniel_err.c
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BL2_SOURCES += ${RDDANIEL_BASE}/rddaniel_plat.c \
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${RDDANIEL_BASE}/rddaniel_security.c \
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${RDDANIEL_BASE}/rddaniel_err.c \
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lib/utils/mem_region.c \
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plat/arm/common/arm_nor_psci_mem_protect.c
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BL31_SOURCES += ${SGI_CPU_SOURCES} \
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${RDDANIEL_BASE}/rddaniel_plat.c \
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${RDDANIEL_BASE}/rddaniel_topology.c \
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drivers/cfi/v2m/v2m_flash.c \
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lib/utils/mem_region.c \
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plat/arm/common/arm_nor_psci_mem_protect.c
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# Add the FDT_SOURCES and options for Dynamic Config
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FDT_SOURCES += ${RDDANIEL_BASE}/fdts/${PLAT}_tb_fw_config.dts
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TB_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_tb_fw_config.dtb
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# Add the TB_FW_CONFIG to FIP and specify the same to certtool
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$(eval $(call TOOL_ADD_PAYLOAD,${TB_FW_CONFIG},--tb-fw-config))
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FDT_SOURCES += ${RDDANIEL_BASE}/fdts/${PLAT}_nt_fw_config.dts
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NT_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_nt_fw_config.dtb
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# Add the NT_FW_CONFIG to FIP and specify the same to certtool
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$(eval $(call TOOL_ADD_PAYLOAD,${NT_FW_CONFIG},--nt-fw-config))
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override CTX_INCLUDE_AARCH32_REGS := 0
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/*
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* Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <plat/arm/common/plat_arm.h>
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/*
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* rddaniel error handler
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*/
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void __dead2 plat_arm_error_handler(int err)
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{
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while (1) {
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wfi();
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}
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}
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/*
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* Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <plat/common/platform.h>
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#include <sgi_plat.h>
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unsigned int plat_arm_sgi_get_platform_id(void)
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{
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return mmio_read_32(SID_REG_BASE + SID_SYSTEM_ID_OFFSET)
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& SID_SYSTEM_ID_PART_NUM_MASK;
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}
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unsigned int plat_arm_sgi_get_config_id(void)
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{
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return mmio_read_32(SID_REG_BASE + SID_SYSTEM_CFG_OFFSET);
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}
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unsigned int plat_arm_sgi_get_multi_chip_mode(void)
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{
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return (mmio_read_32(SID_REG_BASE + SID_NODE_ID_OFFSET) &
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SID_MULTI_CHIP_MODE_MASK) >> SID_MULTI_CHIP_MODE_SHIFT;
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}
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void bl31_platform_setup(void)
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{
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sgi_bl31_common_platform_setup();
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}
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/*
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* Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <platform_def.h>
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/* Initialize the secure environment */
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void plat_arm_security_setup(void)
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{
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}
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/*
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* Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <plat/arm/common/plat_arm.h>
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#include <plat/arm/css/common/css_pm.h>
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/******************************************************************************
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* The power domain tree descriptor.
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******************************************************************************/
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const unsigned char rd_daniel_pd_tree_desc[] = {
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PLAT_ARM_CLUSTER_COUNT,
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CSS_SGI_MAX_CPUS_PER_CLUSTER,
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CSS_SGI_MAX_CPUS_PER_CLUSTER,
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CSS_SGI_MAX_CPUS_PER_CLUSTER,
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CSS_SGI_MAX_CPUS_PER_CLUSTER,
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CSS_SGI_MAX_CPUS_PER_CLUSTER,
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CSS_SGI_MAX_CPUS_PER_CLUSTER,
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CSS_SGI_MAX_CPUS_PER_CLUSTER,
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CSS_SGI_MAX_CPUS_PER_CLUSTER,
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CSS_SGI_MAX_CPUS_PER_CLUSTER,
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CSS_SGI_MAX_CPUS_PER_CLUSTER,
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CSS_SGI_MAX_CPUS_PER_CLUSTER,
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CSS_SGI_MAX_CPUS_PER_CLUSTER,
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CSS_SGI_MAX_CPUS_PER_CLUSTER,
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CSS_SGI_MAX_CPUS_PER_CLUSTER,
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CSS_SGI_MAX_CPUS_PER_CLUSTER,
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CSS_SGI_MAX_CPUS_PER_CLUSTER
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};
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/*******************************************************************************
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* This function returns the topology tree information.
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******************************************************************************/
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const unsigned char *plat_get_power_domain_tree_desc(void)
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{
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return rd_daniel_pd_tree_desc;
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}
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/*******************************************************************************
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* The array mapping platform core position (implemented by plat_my_core_pos())
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* to the SCMI power domain ID implemented by SCP.
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******************************************************************************/
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const uint32_t plat_css_core_pos_to_scmi_dmn_id_map[] = {
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(SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x0)),
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(SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x1)),
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(SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x2)),
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(SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x3)),
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(SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x4)),
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(SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x5)),
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(SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x6)),
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(SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x7)),
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(SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x8)),
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(SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x9)),
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(SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0xA)),
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(SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0xB)),
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(SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0xC)),
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(SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0xD)),
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(SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0xE)),
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(SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0xF))
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};
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/*
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* Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#define SGI_VARIANT_H
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/* SSC_VERSION values for SGI575 */
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#define SGI575_SSC_VER_PART_NUM 0x0783
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#define SGI575_SSC_VER_PART_NUM 0x0783
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/* SID Version values for RD-N1E1-Edge */
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#define RD_N1E1_EDGE_SID_VER_PART_NUM 0x0786
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#define RD_E1_EDGE_CONFIG_ID 0x2
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/* SID Version values for RD-Daniel */
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#define RD_DANIEL_SID_VER_PART_NUM 0x078a
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/* Structure containing SGI platform variant information */
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typedef struct sgi_platform_info {
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unsigned int platform_id; /* Part Number of the platform */
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scmi_channel_plat_info_t *plat_css_get_scmi_info(int channel_id)
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{
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if (sgi_plat_info.platform_id == RD_N1E1_EDGE_SID_VER_PART_NUM) {
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if (sgi_plat_info.platform_id == RD_N1E1_EDGE_SID_VER_PART_NUM ||
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sgi_plat_info.platform_id == RD_DANIEL_SID_VER_PART_NUM) {
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if (channel_id >= sizeof(rd_n1e1_edge_scmi_plat_info))
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panic();
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return &rd_n1e1_edge_scmi_plat_info[channel_id];
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const plat_psci_ops_t *plat_arm_psci_override_pm_ops(plat_psci_ops_t *ops)
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{
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/* For RD-E1-Edge platform only CPU ON/OFF is supported */
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if ((sgi_plat_info.platform_id == RD_N1E1_EDGE_SID_VER_PART_NUM) &&
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(sgi_plat_info.config_id == RD_E1_EDGE_CONFIG_ID)) {
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/*
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* For RD-E1-Edge and RD-Daniel platforms, only CPU power ON/OFF
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* PSCI platform callbacks are supported.
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*/
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if (((sgi_plat_info.platform_id == RD_N1E1_EDGE_SID_VER_PART_NUM) &&
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(sgi_plat_info.config_id == RD_E1_EDGE_CONFIG_ID)) ||
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(sgi_plat_info.platform_id == RD_DANIEL_SID_VER_PART_NUM)) {
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ops->cpu_standby = NULL;
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ops->system_off = NULL;
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ops->system_reset = NULL;
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