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Merge changes I99a5d96f,I89b950f0 into integration 

* changes:
  lib/cpus: update MIDR value for rainier cpu
  fdts: enable virtio-rng component for morello fvp platform
This commit is contained in:
Manish Pandey 2020-10-09 11:09:19 +00:00 committed by TrustedFirmware Code Review
parent eff2edeed7 3e0a861e3c
commit 210ac186ad
2 changed files with 7 additions and 1 deletions
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6
fdts/morello-fvp.dts
View File

@ -80,6 +80,12 @@
interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
};
virtio_rng@1c190000 {
compatible = "virtio,mmio","virtio-rng";
reg = <0x0 0x1c190000 0x0 0x200>;
interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
};
ethernet@1d100000 {
compatible = "smsc,lan91c111";
reg = <0x0 0x1d100000 0x0 0x10000>;

2
include/lib/cpus/aarch64/rainier.h
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@ -10,7 +10,7 @@
#include <lib/utils_def.h>
/* RAINIER MIDR for revision 0 */
#define RAINIER_MIDR U(0x3f0f4100)
#define RAINIER_MIDR U(0x3f0f4120)
/* Exception Syndrome register EC code for IC Trap */
#define RAINIER_EC_IC_TRAP U(0x1f)