From 214e8464acd27b41d5e81b94e42b7bf33a54fb40 Mon Sep 17 00:00:00 2001 From: Anthony Zhou Date: Fri, 3 Mar 2017 16:23:08 +0800 Subject: [PATCH] Tegra186: PM: fix MISRA defects in plat_psci_handlers.c Main fixes: Added explicit casts (e.g. 0U) to integers in order for them to be compatible with whatever operation they're used in [Rule 10.1] convert object type to match the type of function parameters [Rule 10.3] Force operands of an operator to the same type category [Rule 10.4] Fix implicit widening of composite assignment [Rule 10.6] Change-Id: I5840a07f37beefc3326ac56d0b4a4701602bd8a8 Signed-off-by: Anthony Zhou --- plat/nvidia/tegra/include/tegra_private.h | 2 +- .../tegra/soc/t186/plat_psci_handlers.c | 184 ++++++++++-------- 2 files changed, 105 insertions(+), 81 deletions(-) diff --git a/plat/nvidia/tegra/include/tegra_private.h b/plat/nvidia/tegra/include/tegra_private.h index d0028e01a..0267e08c4 100644 --- a/plat/nvidia/tegra/include/tegra_private.h +++ b/plat/nvidia/tegra/include/tegra_private.h @@ -54,7 +54,7 @@ struct tegra_bl31_params { }; /* Declarations for plat_psci_handlers.c */ -int32_t tegra_soc_validate_power_state(unsigned int power_state, +int32_t tegra_soc_validate_power_state(uint32_t power_state, psci_power_state_t *req_state); /* Declarations for plat_setup.c */ diff --git a/plat/nvidia/tegra/soc/t186/plat_psci_handlers.c b/plat/nvidia/tegra/soc/t186/plat_psci_handlers.c index 3a1227a2d..7a9ce287a 100644 --- a/plat/nvidia/tegra/soc/t186/plat_psci_handlers.c +++ b/plat/nvidia/tegra/soc/t186/plat_psci_handlers.c @@ -30,29 +30,33 @@ extern void tegra186_cpu_reset_handler(void); extern uint32_t __tegra186_cpu_reset_handler_end, __tegra186_smmu_context; +/* TZDRAM offset for saving SMMU context */ +#define TEGRA186_SMMU_CTX_OFFSET 16UL + /* state id mask */ -#define TEGRA186_STATE_ID_MASK 0xF +#define TEGRA186_STATE_ID_MASK 0xFU /* constants to get power state's wake time */ -#define TEGRA186_WAKE_TIME_MASK 0x0FFFFFF0 -#define TEGRA186_WAKE_TIME_SHIFT 4 +#define TEGRA186_WAKE_TIME_MASK 0x0FFFFFF0U +#define TEGRA186_WAKE_TIME_SHIFT 4U /* default core wake mask for CPU_SUSPEND */ -#define TEGRA186_CORE_WAKE_MASK 0x180c +#define TEGRA186_CORE_WAKE_MASK 0x180cU /* context size to save during system suspend */ -#define TEGRA186_SE_CONTEXT_SIZE 3 +#define TEGRA186_SE_CONTEXT_SIZE 3U static uint32_t se_regs[TEGRA186_SE_CONTEXT_SIZE]; -static struct t18x_psci_percpu_data { - unsigned int wake_time; -} __aligned(CACHE_WRITEBACK_GRANULE) percpu_data[PLATFORM_CORE_COUNT]; +static struct tegra_psci_percpu_data { + uint32_t wake_time; +} __aligned(CACHE_WRITEBACK_GRANULE) tegra_percpu_data[PLATFORM_CORE_COUNT]; -int32_t tegra_soc_validate_power_state(unsigned int power_state, +int32_t tegra_soc_validate_power_state(uint32_t power_state, psci_power_state_t *req_state) { - int state_id = psci_get_pstate_id(power_state) & TEGRA186_STATE_ID_MASK; - int cpu = plat_my_core_pos(); + uint8_t state_id = (uint8_t)psci_get_pstate_id(power_state) & TEGRA186_STATE_ID_MASK; + uint32_t cpu = plat_my_core_pos(); + int32_t ret = PSCI_E_SUCCESS; /* save the core wake time (in TSC ticks)*/ - percpu_data[cpu].wake_time = (power_state & TEGRA186_WAKE_TIME_MASK) + tegra_percpu_data[cpu].wake_time = (power_state & TEGRA186_WAKE_TIME_MASK) << TEGRA186_WAKE_TIME_SHIFT; /* @@ -62,8 +66,8 @@ int32_t tegra_soc_validate_power_state(unsigned int power_state, * from DRAM in that function, because the L2 cache is not flushed * unless the cluster is entering CC6/CC7. */ - clean_dcache_range((uint64_t)&percpu_data[cpu], - sizeof(percpu_data[cpu])); + clean_dcache_range((uint64_t)&tegra_percpu_data[cpu], + sizeof(tegra_percpu_data[cpu])); /* Sanity check the requested state id */ switch (state_id) { @@ -78,18 +82,19 @@ int32_t tegra_soc_validate_power_state(unsigned int power_state, default: ERROR("%s: unsupported state id (%d)\n", __func__, state_id); - return PSCI_E_INVALID_PARAMS; + ret = PSCI_E_INVALID_PARAMS; + break; } - return PSCI_E_SUCCESS; + return ret; } -int tegra_soc_pwr_domain_suspend(const psci_power_state_t *target_state) +int32_t tegra_soc_pwr_domain_suspend(const psci_power_state_t *target_state) { const plat_local_state_t *pwr_domain_state; - unsigned int stateid_afflvl0, stateid_afflvl2; - int cpu = plat_my_core_pos(); - plat_params_from_bl2_t *params_from_bl2 = bl31_get_plat_params(); + uint8_t stateid_afflvl0, stateid_afflvl2; + uint32_t cpu = plat_my_core_pos(); + const plat_params_from_bl2_t *params_from_bl2 = bl31_get_plat_params(); mce_cstate_info_t cstate_info = { 0 }; uint64_t smmu_ctx_base; uint32_t val; @@ -107,8 +112,8 @@ int tegra_soc_pwr_domain_suspend(const psci_power_state_t *target_state) /* Enter CPU idle/powerdown */ val = (stateid_afflvl0 == PSTATE_ID_CORE_IDLE) ? TEGRA_ARI_CORE_C6 : TEGRA_ARI_CORE_C7; - (void)mce_command_handler(MCE_CMD_ENTER_CSTATE, val, - percpu_data[cpu].wake_time, 0); + (void)mce_command_handler((uint64_t)MCE_CMD_ENTER_CSTATE, (uint64_t)val, + tegra_percpu_data[cpu].wake_time, 0U); } else if (stateid_afflvl2 == PSTATE_ID_SOC_POWERDN) { @@ -136,18 +141,20 @@ int tegra_soc_pwr_domain_suspend(const psci_power_state_t *target_state) cstate_info.system_state_force = 1; cstate_info.update_wake_mask = 1; mce_update_cstate_info(&cstate_info); - /* Loop until system suspend is allowed */ do { - val = mce_command_handler(MCE_CMD_IS_SC7_ALLOWED, + val = (uint32_t)mce_command_handler( + (uint64_t)MCE_CMD_IS_SC7_ALLOWED, TEGRA_ARI_CORE_C7, MCE_CORE_SLEEP_TIME_INFINITE, - 0); - } while (val == 0); + 0U); + } while (val == 0U); /* Instruct the MCE to enter system suspend state */ - (void)mce_command_handler(MCE_CMD_ENTER_CSTATE, - TEGRA_ARI_CORE_C7, MCE_CORE_SLEEP_TIME_INFINITE, 0); + (void)mce_command_handler((uint64_t)MCE_CMD_ENTER_CSTATE, + TEGRA_ARI_CORE_C7, MCE_CORE_SLEEP_TIME_INFINITE, 0U); + } else { + ; /* do nothing */ } return PSCI_E_SUCCESS; @@ -157,23 +164,28 @@ int tegra_soc_pwr_domain_suspend(const psci_power_state_t *target_state) * Platform handler to calculate the proper target power level at the * specified affinity level ******************************************************************************/ -plat_local_state_t tegra_soc_get_target_pwr_state(unsigned int lvl, +plat_local_state_t tegra_soc_get_target_pwr_state(uint32_t lvl, const plat_local_state_t *states, - unsigned int ncpu) + uint32_t ncpu) { plat_local_state_t target = *states; - int cpu = plat_my_core_pos(), ret, cluster_powerdn = 1; - int core_pos = read_mpidr() & MPIDR_CPU_MASK; + uint32_t pos = 0; + plat_local_state_t result = PSCI_LOCAL_STATE_RUN; + uint32_t cpu = plat_my_core_pos(), num_cpu = ncpu; + int32_t ret, cluster_powerdn = 1; + uint64_t core_pos = read_mpidr() & (uint64_t)MPIDR_CPU_MASK; mce_cstate_info_t cstate_info = { 0 }; /* get the power state at this level */ - if (lvl == MPIDR_AFFLVL1) - target = *(states + core_pos); - if (lvl == MPIDR_AFFLVL2) - target = *(states + cpu); + if (lvl == (uint32_t)MPIDR_AFFLVL1) { + target = states[core_pos]; + } + if (lvl == (uint32_t)MPIDR_AFFLVL2) { + target = states[cpu]; + } /* CPU suspend */ - if (lvl == MPIDR_AFFLVL1 && target == PSTATE_ID_CORE_POWERDN) { + if ((lvl == (uint32_t)MPIDR_AFFLVL1) && (target == PSTATE_ID_CORE_POWERDN)) { /* Program default wake mask */ cstate_info.wake_mask = TEGRA186_CORE_WAKE_MASK; @@ -181,25 +193,29 @@ plat_local_state_t tegra_soc_get_target_pwr_state(unsigned int lvl, mce_update_cstate_info(&cstate_info); /* Check if CCx state is allowed. */ - ret = mce_command_handler(MCE_CMD_IS_CCX_ALLOWED, - TEGRA_ARI_CORE_C7, percpu_data[cpu].wake_time, - 0); - if (ret) - return PSTATE_ID_CORE_POWERDN; + ret = mce_command_handler((uint64_t)MCE_CMD_IS_CCX_ALLOWED, + TEGRA_ARI_CORE_C7, tegra_percpu_data[cpu].wake_time, + 0U); + if (ret != 0) { + result = PSTATE_ID_CORE_POWERDN; + } } /* CPU off */ - if (lvl == MPIDR_AFFLVL1 && target == PLAT_MAX_OFF_STATE) { + if ((lvl == (uint32_t)MPIDR_AFFLVL1) && (target == PLAT_MAX_OFF_STATE)) { /* find out the number of ON cpus in the cluster */ do { - target = *states++; - if (target != PLAT_MAX_OFF_STATE) + target = states[pos]; + if (target != PLAT_MAX_OFF_STATE) { cluster_powerdn = 0; - } while (--ncpu); + } + --num_cpu; + pos++; + } while (num_cpu != 0U); /* Enable cluster powerdn from last CPU in the cluster */ - if (cluster_powerdn) { + if (cluster_powerdn != 0) { /* Enable CC7 state and turn off wake mask */ cstate_info.cluster = TEGRA_ARI_CLUSTER_CC7; @@ -207,12 +223,13 @@ plat_local_state_t tegra_soc_get_target_pwr_state(unsigned int lvl, mce_update_cstate_info(&cstate_info); /* Check if CCx state is allowed. */ - ret = mce_command_handler(MCE_CMD_IS_CCX_ALLOWED, + ret = mce_command_handler((uint64_t)MCE_CMD_IS_CCX_ALLOWED, TEGRA_ARI_CORE_C7, MCE_CORE_SLEEP_TIME_INFINITE, - 0); - if (ret) - return PSTATE_ID_CORE_POWERDN; + 0U); + if (ret != 0) { + result = PSTATE_ID_CORE_POWERDN; + } } else { @@ -223,20 +240,21 @@ plat_local_state_t tegra_soc_get_target_pwr_state(unsigned int lvl, } /* System Suspend */ - if (((lvl == MPIDR_AFFLVL2) || (lvl == MPIDR_AFFLVL1)) && - (target == PSTATE_ID_SOC_POWERDN)) - return PSTATE_ID_SOC_POWERDN; + if (((lvl == (uint32_t)MPIDR_AFFLVL2) || (lvl == (uint32_t)MPIDR_AFFLVL1)) && + (target == PSTATE_ID_SOC_POWERDN)) { + result = PSTATE_ID_SOC_POWERDN; + } /* default state */ - return PSCI_LOCAL_STATE_RUN; + return result; } -int tegra_soc_pwr_domain_power_down_wfi(const psci_power_state_t *target_state) +int32_t tegra_soc_pwr_domain_power_down_wfi(const psci_power_state_t *target_state) { const plat_local_state_t *pwr_domain_state = target_state->pwr_domain_state; - plat_params_from_bl2_t *params_from_bl2 = bl31_get_plat_params(); - unsigned int stateid_afflvl2 = pwr_domain_state[PLAT_MAX_PWR_LVL] & + const plat_params_from_bl2_t *params_from_bl2 = bl31_get_plat_params(); + uint8_t stateid_afflvl2 = pwr_domain_state[PLAT_MAX_PWR_LVL] & TEGRA186_STATE_ID_MASK; uint64_t val; @@ -248,7 +266,7 @@ int tegra_soc_pwr_domain_power_down_wfi(const psci_power_state_t *target_state) */ val = params_from_bl2->tzdram_base + ((uintptr_t)&__tegra186_cpu_reset_handler_end - - (uintptr_t)tegra186_cpu_reset_handler); + (uintptr_t)&tegra186_cpu_reset_handler); memcpy16((void *)(uintptr_t)val, (void *)(uintptr_t)BL31_BASE, (uintptr_t)&__BL31_END__ - (uintptr_t)BL31_BASE); } @@ -256,29 +274,32 @@ int tegra_soc_pwr_domain_power_down_wfi(const psci_power_state_t *target_state) return PSCI_E_SUCCESS; } -int tegra_soc_pwr_domain_on(u_register_t mpidr) +int32_t tegra_soc_pwr_domain_on(u_register_t mpidr) { - uint32_t target_cpu = mpidr & MPIDR_CPU_MASK; + uint32_t target_cpu = mpidr & (uint64_t)MPIDR_CPU_MASK; uint32_t target_cluster = (mpidr & MPIDR_CLUSTER_MASK) >> - MPIDR_AFFINITY_BITS; + (uint64_t)MPIDR_AFFINITY_BITS; + int32_t ret = PSCI_E_SUCCESS; + + if (target_cluster > (uint64_t)MPIDR_AFFLVL1) { - if (target_cluster > MPIDR_AFFLVL1) { ERROR("%s: unsupported CPU (0x%lx)\n", __func__, mpidr); - return PSCI_E_NOT_PRESENT; + ret = PSCI_E_NOT_PRESENT; + + } else { + /* construct the target CPU # */ + target_cpu |= (target_cluster << 2); + + (void)mce_command_handler((uint64_t)MCE_CMD_ONLINE_CORE, target_cpu, 0U, 0U); } - /* construct the target CPU # */ - target_cpu |= (target_cluster << 2); - - mce_command_handler(MCE_CMD_ONLINE_CORE, target_cpu, 0, 0); - - return PSCI_E_SUCCESS; + return ret; } -int tegra_soc_pwr_domain_on_finish(const psci_power_state_t *target_state) +int32_t tegra_soc_pwr_domain_on_finish(const psci_power_state_t *target_state) { - int stateid_afflvl2 = target_state->pwr_domain_state[PLAT_MAX_PWR_LVL]; - int stateid_afflvl0 = target_state->pwr_domain_state[MPIDR_AFFLVL0]; + uint8_t stateid_afflvl2 = target_state->pwr_domain_state[PLAT_MAX_PWR_LVL]; + uint8_t stateid_afflvl0 = target_state->pwr_domain_state[MPIDR_AFFLVL0]; mce_cstate_info_t cstate_info = { 0 }; uint64_t impl, val; const plat_params_from_bl2_t *plat_params = bl31_get_plat_params(); @@ -293,7 +314,7 @@ int tegra_soc_pwr_domain_on_finish(const psci_power_state_t *target_state) (impl != (uint64_t)DENVER_IMPL)) { val = read_l2ctlr_el1(); - val |= (uint64_t)CORTEX_A57_L2_ECC_PARITY_PROTECTION_BIT; + val |= CORTEX_A57_L2_ECC_PARITY_PROTECTION_BIT; write_l2ctlr_el1(val); } @@ -342,17 +363,20 @@ int tegra_soc_pwr_domain_on_finish(const psci_power_state_t *target_state) return PSCI_E_SUCCESS; } -int tegra_soc_pwr_domain_off(const psci_power_state_t *target_state) +int32_t tegra_soc_pwr_domain_off(const psci_power_state_t *target_state) { - int impl = (read_midr() >> MIDR_IMPL_SHIFT) & MIDR_IMPL_MASK; + uint64_t impl = (read_midr() >> MIDR_IMPL_SHIFT) & (uint64_t)MIDR_IMPL_MASK; + + (void)target_state; /* Disable Denver's DCO operations */ - if (impl == DENVER_IMPL) + if (impl == DENVER_IMPL) { denver_disable_dco(); + } /* Turn off CPU */ - (void)mce_command_handler(MCE_CMD_ENTER_CSTATE, TEGRA_ARI_CORE_C7, - MCE_CORE_SLEEP_TIME_INFINITE, 0); + (void)mce_command_handler((uint64_t)MCE_CMD_ENTER_CSTATE, TEGRA_ARI_CORE_C7, + MCE_CORE_SLEEP_TIME_INFINITE, 0U); return PSCI_E_SUCCESS; } @@ -370,7 +394,7 @@ __dead2 void tegra_soc_prepare_system_off(void) } } -int tegra_soc_prepare_system_reset(void) +int32_t tegra_soc_prepare_system_reset(void) { mce_enter_ccplex_state(TEGRA_ARI_MISC_CCPLEX_SHUTDOWN_REBOOT);