Merge changes from topic "fpga_generic" into integration
* changes: arm_fpga: Add platform documentation arm_fpga: Add post-build linker script arm_fpga: Add ROM trampoline arm_fpga: Add devicetree file arm_fpga: Remove SPE PMU DT node if SPE is not available arm_fpga: Adjust GICR size in DT to match number of cores fdt: Add function to adjust GICv3 redistributor size drivers: arm: gicv3: Allow detecting number of cores
This commit is contained in:
André Przywara
TrustedFirmware Code Review
commit
2173b3e05f
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@ -377,3 +377,64 @@ int fdt_add_cpus_node(void *dtb, unsigned int afflv0,
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return offs;
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}
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/**
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* fdt_adjust_gic_redist() - Adjust GICv3 redistributor size
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* @dtb: Pointer to the DT blob in memory
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* @nr_cores: Number of CPU cores on this system.
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* @gicr_frame_size: Size of the GICR frame per core
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*
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* On a GICv3 compatible interrupt controller, the redistributor provides
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* a number of 64k pages per each supported core. So with a dynamic topology,
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* this size cannot be known upfront and thus can't be hardcoded into the DTB.
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*
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* Find the DT node describing the GICv3 interrupt controller, and adjust
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* the size of the redistributor to match the number of actual cores on
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* this system.
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* A GICv4 compatible redistributor uses four 64K pages per core, whereas GICs
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* without support for direct injection of virtual interrupts use two 64K pages.
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* The @gicr_frame_size parameter should be 262144 and 131072, respectively.
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*
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* Return: 0 on success, negative error value otherwise.
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*/
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int fdt_adjust_gic_redist(void *dtb, unsigned int nr_cores,
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unsigned int gicr_frame_size)
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{
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int offset = fdt_node_offset_by_compatible(dtb, 0, "arm,gic-v3");
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uint64_t redist_size_64;
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uint32_t redist_size_32;
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void *val;
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int parent;
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int ac, sc;
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if (offset < 0) {
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return offset;
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}
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parent = fdt_parent_offset(dtb, offset);
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if (parent < 0) {
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return parent;
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}
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ac = fdt_address_cells(dtb, parent);
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sc = fdt_size_cells(dtb, parent);
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if (ac < 0 || sc < 0) {
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return -EINVAL;
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}
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if (sc == 1) {
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redist_size_32 = cpu_to_fdt32(nr_cores * gicr_frame_size);
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val = &redist_size_32;
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} else {
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redist_size_64 = cpu_to_fdt64(nr_cores * gicr_frame_size);
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val = &redist_size_64;
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}
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/*
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* The redistributor is described in the second "reg" entry.
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* So we have to skip one address and one size cell, then another
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* address cell to get to the second size cell.
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*/
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return fdt_setprop_inplace_namelen_partial(dtb, offset, "reg", 3,
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(ac + sc + ac) * 4,
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val, sc * 4);
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}
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@ -0,0 +1,97 @@
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Arm FPGA Platform
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=================
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This platform supports FPGA images used internally in Arm Ltd., for
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testing and bringup of new cores. With that focus, peripheral support is
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minimal: there is no mass storage or display output, for instance. Also
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this port ignores any power management features of the platform.
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Some interconnect setup is done internally by the platform, so the TF-A code
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just needs to setup UART and GIC.
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The FPGA platform requires to pass on a DTB for the non-secure payload
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(mostly Linux), so we let TF-A use information from the DTB for dynamic
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configuration: the UART and GIC base addresses are read from there.
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As a result this port is a fairly generic BL31-only port, which can serve
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as a template for a minimal new (and possibly DT-based) platform port.
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The aim of this port is to support as many FPGA images as possible with
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a single build. Image specific data must be described in the DTB or should
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be auto-detected at runtime.
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As the number and topology layout of the CPU cores differs significantly
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across the various images, this is detected at runtime by BL31.
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The /cpus node in the DT will be added and filled accordingly, as long as
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it does not exist already.
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Platform-specific build options
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-------------------------------
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- ``SUPPORT_UNKNOWN_MPID`` : Boolean option to allow unknown MPIDR registers.
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Normally TF-A panics if it encounters a MPID value not matched to its
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internal list, but for new or experimental cores this creates a lot of
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churn. With this option, the code will fall back to some basic CPU support
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code (only architectural system registers, and no errata).
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Default value of this flag is 1.
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- ``PRELOADED_BL33_BASE`` : Physical address of the BL33 non-secure payload.
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It must have been loaded into DRAM already, typically this is done by
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the script that also loads BL31 and the DTB.
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It defaults to 0x80080000, which is the traditional load address for an
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arm64 Linux kernel.
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- ``FPGA_PRELOADED_DTB_BASE`` : Physical address of the flattened device
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tree blob (DTB). This DT will be used by TF-A for dynamic configuration,
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so it must describe at least the UART and a GICv3 interrupt controller.
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The DT gets amended by the code, to potentially add a command line and
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fill the CPU topology nodes. It will also be passed on to BL33, by
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putting its address into the x0 register before jumping to the entry
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point (following the Linux kernel boot protocol).
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It defaults to 0x80070000, which is 64KB before the BL33 load address.
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- ``FPGA_PRELOADED_CMD_LINE`` : Physical address of the command line to
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put into the devicetree blob. Due to the lack of a proper bootloader,
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a command line can be put somewhere into memory, so that BL31 will
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detect it and copy it into the DTB passed on to BL33.
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To avoid random garbage, there needs to be a "CMD:" signature before the
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actual command line.
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Defaults to 0x1000, which is normally in the "ROM" space of the typical
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FPGA image (which can be written by the FPGA payload uploader, but is
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read-only to the CPU). The FPGA payload tool should be given a text file
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containing the desired command line, prefixed by the "CMD:" signature.
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Building the TF-A image
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-----------------------
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.. code:: shell
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make PLAT=arm_fgpa DEBUG=1
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This will use the default load addresses as described above. When those
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addresses need to differ for a certain setup, they can be passed on the
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make command line:
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.. code:: shell
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make PLAT=arm_fgpa DEBUG=1 PRELOADED_BL33_BASE=0x80200000 FPGA_PRELOADED_DTB_BASE=0x80180000 bl31
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Running the TF-A image
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----------------------
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After building TF-A, the actual TF-A code will be located in ``bl31.bin`` in
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the build directory.
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Additionally there is a ``bl31.axf`` ELF file, which contains BL31, as well
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as some simple ROM trampoline code (required by the Arm FPGA boot flow) and
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a generic DTB to support most of the FPGA images. This can be simply handed
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over to the FPGA payload uploader, which will take care of loading the
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components at their respective load addresses. In addition to this file
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you need at least a BL33 payload (typically a Linux kernel image), optionally
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a Linux initrd image file and possibly a command line:
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.. code:: shell
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fpga-run ... -m bl31.axf -l auto -m Image -l 0x80080000 -m initrd.gz -l 0x84000000 -m cmdline.txt -l 0x1000
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--------------
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*Copyright (c) 2020, Arm Limited. All rights reserved.*
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@ -9,6 +9,7 @@ Arm Development Platforms
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fvp/index
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fvp-ve/index
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tc0/index
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arm_fpga/index
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arm-build-options
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This chapter holds documentation related to Arm's development platforms,
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@ -326,3 +326,33 @@ unsigned int gicv3_secure_ppi_sgi_config_props(uintptr_t gicr_base,
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return ctlr_enable;
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}
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/**
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* gicv3_rdistif_get_number_frames() - determine size of GICv3 GICR region
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* @gicr_frame: base address of the GICR region to check
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*
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* This iterates over the GICR_TYPER registers of multiple GICR frames in
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* a GICR region, to find the instance which has the LAST bit set. For most
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* systems this corresponds to the number of cores handled by a redistributor,
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* but there could be disabled cores among them.
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* It assumes that each GICR region is fully accessible (till the LAST bit
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* marks the end of the region).
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* If a platform has multiple GICR regions, this function would need to be
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* called multiple times, providing the respective GICR base address each time.
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*
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* Return: number of valid GICR frames (at least 1, up to PLATFORM_CORE_COUNT)
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******************************************************************************/
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unsigned int gicv3_rdistif_get_number_frames(const uintptr_t gicr_frame)
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{
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uintptr_t rdistif_base = gicr_frame;
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unsigned int count;
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for (count = 1; count < PLATFORM_CORE_COUNT; count++) {
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if ((gicr_read_typer(rdistif_base) & TYPER_LAST_BIT) != 0U) {
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break;
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}
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rdistif_base += (1U << GICR_PCPUBASE_SHIFT);
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}
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return count;
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}
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@ -0,0 +1,102 @@
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// SPDX-License-Identifier: (GPL-2.0 or BSD-3-Clause)
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/*
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* Copyright (c) 2020, Arm Limited. All rights reserved.
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*
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* Devicetree for the Arm Ltd. FPGA platform
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* Number and kind of CPU cores differs from image to image, so the
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* topology is auto-detected by BL31, and the /cpus node is created and
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* populated accordingly at runtime.
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*/
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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/dts-v1/;
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/ {
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model = "ARM FPGA";
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compatible = "arm,fpga", "arm,vexpress";
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interrupt-parent = <&gic>;
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#address-cells = <2>;
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#size-cells = <2>;
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aliases {
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serial0 = &dbg_uart;
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};
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chosen {
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stdout-path = "serial0:38400n8";
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bootargs = "console=ttyAMA0,38400n8 earlycon";
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/* Allow to upload a generous 100MB initrd payload. */
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linux,initrd-start = <0x0 0x84000000>;
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linux,initrd-end = <0x0 0x85400000>;
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};
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/* /cpus node will be added by BL31 at runtime. */
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psci {
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compatible = "arm,psci-0.2";
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method = "smc";
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};
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timer {
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compatible = "arm,armv8-timer";
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clock-frequency = <10000000>;
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interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
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<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
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<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
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<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
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};
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pmu {
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compatible = "arm,armv8-pmuv3";
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interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
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};
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/* This node will be removed at runtime on cores without SPE. */
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spe-pmu {
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compatible = "arm,statistical-profiling-extension-v1";
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interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>;
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};
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memory@80000000 {
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device_type = "memory";
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reg = <0x0 0x80000000 0x0 0x80000000>,
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<0x8 0x80000000 0x1 0x80000000>;
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};
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bus_refclk: refclk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <100000000>;
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clock-output-names = "apb_pclk";
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};
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uartclk: baudclock {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <10000000>;
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clock-output-names = "uartclk";
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};
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dbg_uart: serial@7ff80000 {
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compatible = "arm,pl011", "arm,primecell";
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reg = <0x0 0x7ff80000 0x0 0x00001000>;
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interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&uartclk>, <&bus_refclk>;
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clock-names = "uartclk", "apb_pclk";
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};
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gic: interrupt-controller@30000000 {
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compatible = "arm,gic-v3";
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#address-cells = <2>;
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#interrupt-cells = <3>;
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#size-cells = <2>;
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ranges;
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interrupt-controller;
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reg = <0x0 0x30000000 0x0 0x00010000>, /* GICD */
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/* The GICR size will be adjusted at runtime to match the cores. */
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<0x0 0x30040000 0x0 0x00020000>; /* GICR for one core */
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interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
|
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};
|
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};
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|
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@ -13,5 +13,7 @@ int fdt_add_reserved_memory(void *dtb, const char *node_name,
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uintptr_t base, size_t size);
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int fdt_add_cpus_node(void *dtb, unsigned int afflv0,
|
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unsigned int afflv1, unsigned int afflv2);
|
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int fdt_adjust_gic_redist(void *dtb, unsigned int nr_cores,
|
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unsigned int gicr_frame_size);
|
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|
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#endif /* FDT_FIXUP_H */
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|
|
|
|||
|
|
@ -488,6 +488,7 @@ void gicv3_distif_init(void);
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void gicv3_rdistif_init(unsigned int proc_num);
|
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void gicv3_rdistif_on(unsigned int proc_num);
|
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void gicv3_rdistif_off(unsigned int proc_num);
|
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unsigned int gicv3_rdistif_get_number_frames(const uintptr_t gicr_frame);
|
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void gicv3_cpuif_enable(unsigned int proc_num);
|
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void gicv3_cpuif_disable(unsigned int proc_num);
|
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unsigned int gicv3_get_pending_interrupt_type(void);
|
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|
|
|
|||
|
|
@ -0,0 +1,47 @@
|
|||
/*
|
||||
* Copyright (c) 2020, ARM Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*
|
||||
* Linker script for the Arm Ltd. FPGA boards to generate an ELF file that
|
||||
* contains the ROM trampoline, BL31 and the DTB.
|
||||
*
|
||||
* This allows to pass just one file to the uploader tool, and automatically
|
||||
* provides the correct load addresses.
|
||||
*/
|
||||
|
||||
#include <platform_def.h>
|
||||
|
||||
OUTPUT_FORMAT("elf64-littleaarch64")
|
||||
OUTPUT_ARCH(aarch64)
|
||||
|
||||
INPUT(./bl31/bl31.elf)
|
||||
INPUT(./rom_trampoline.o)
|
||||
|
||||
TARGET(binary)
|
||||
INPUT(./fdts/arm_fpga.dtb)
|
||||
|
||||
ENTRY(_start)
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
.rom (0x0): {
|
||||
*rom_trampoline.o(.text*)
|
||||
KEEP(*(.rom))
|
||||
}
|
||||
|
||||
.bl31 (BL31_BASE): {
|
||||
ASSERT(. == ALIGN(PAGE_SIZE), "BL31_BASE is not page aligned");
|
||||
*bl31.elf(.text* .data* .rodata* ro* .bss*)
|
||||
*bl31.elf(.stack)
|
||||
}
|
||||
|
||||
.dtb (FPGA_PRELOADED_DTB_BASE): {
|
||||
ASSERT(. == ALIGN(8), "DTB address is not 8-byte aligned");
|
||||
*arm_fpga.dtb
|
||||
}
|
||||
|
||||
/DISCARD/ : { *(.debug_*) }
|
||||
/DISCARD/ : { *(.note*) }
|
||||
/DISCARD/ : { *(.comment*) }
|
||||
}
|
||||
|
|
@ -9,8 +9,10 @@
|
|||
|
||||
#include <common/fdt_fixup.h>
|
||||
#include <common/fdt_wrappers.h>
|
||||
#include <drivers/arm/gicv3.h>
|
||||
#include <drivers/delay_timer.h>
|
||||
#include <drivers/generic_delay_timer.h>
|
||||
#include <lib/extensions/spe.h>
|
||||
#include <libfdt.h>
|
||||
|
||||
#include "fpga_private.h"
|
||||
|
|
@ -210,6 +212,26 @@ static void fpga_prepare_dtb(void)
|
|||
if (err < 0) {
|
||||
ERROR("Error %d creating the /cpus DT node\n", err);
|
||||
panic();
|
||||
} else {
|
||||
unsigned int nr_cores = fpga_get_nr_gic_cores();
|
||||
|
||||
INFO("Adjusting GICR DT region to cover %u cores\n",
|
||||
nr_cores);
|
||||
err = fdt_adjust_gic_redist(fdt, nr_cores,
|
||||
1U << GICR_PCPUBASE_SHIFT);
|
||||
if (err < 0) {
|
||||
ERROR("Error %d fixing up GIC DT node\n", err);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* Check whether we support the SPE PMU. Remove the DT node if not. */
|
||||
if (!spe_supported()) {
|
||||
int node = fdt_node_offset_by_compatible(fdt, 0,
|
||||
"arm,statistical-profiling-extension-v1");
|
||||
|
||||
if (node >= 0) {
|
||||
fdt_del_node(fdt, node);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -77,3 +77,8 @@ void fpga_pwr_gic_off(void)
|
|||
gicv3_cpuif_disable(plat_my_core_pos());
|
||||
gicv3_rdistif_off(plat_my_core_pos());
|
||||
}
|
||||
|
||||
unsigned int fpga_get_nr_gic_cores(void)
|
||||
{
|
||||
return gicv3_rdistif_get_number_frames(fpga_gicv3_driver_data.gicr_base);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -24,6 +24,7 @@ void plat_fpga_gic_init(void);
|
|||
void fpga_pwr_gic_on_finish(void);
|
||||
void fpga_pwr_gic_off(void);
|
||||
unsigned int plat_fpga_calc_core_pos(uint32_t mpid);
|
||||
unsigned int fpga_get_nr_gic_cores(void);
|
||||
|
||||
#endif /* __ASSEMBLER__ */
|
||||
|
||||
|
|
|
|||
|
|
@ -89,6 +89,8 @@ FPGA_GIC_SOURCES := ${GICV3_SOURCES} \
|
|||
plat/common/plat_gicv3.c \
|
||||
plat/arm/board/arm_fpga/fpga_gicv3.c
|
||||
|
||||
FDT_SOURCES := fdts/arm_fpga.dts
|
||||
|
||||
PLAT_INCLUDES := -Iplat/arm/board/arm_fpga/include
|
||||
|
||||
PLAT_BL_COMMON_SOURCES := plat/arm/board/arm_fpga/${ARCH}/fpga_helpers.S
|
||||
|
|
@ -106,4 +108,11 @@ BL31_SOURCES += common/fdt_wrappers.c \
|
|||
${FPGA_CPU_LIBS} \
|
||||
${FPGA_GIC_SOURCES}
|
||||
|
||||
all: bl31
|
||||
$(eval $(call MAKE_S,$(BUILD_PLAT),plat/arm/board/arm_fpga/rom_trampoline.S,31))
|
||||
$(eval $(call MAKE_LD,$(BUILD_PLAT)/build_axf.ld,plat/arm/board/arm_fpga/build_axf.ld.S,31))
|
||||
|
||||
bl31.axf: bl31 dtbs ${BUILD_PLAT}/rom_trampoline.o ${BUILD_PLAT}/build_axf.ld
|
||||
$(ECHO) " LD $@"
|
||||
$(Q)$(LD) -T ${BUILD_PLAT}/build_axf.ld -L ${BUILD_PLAT} --strip-debug -o ${BUILD_PLAT}/bl31.axf
|
||||
|
||||
all: bl31.axf
|
||||
|
|
|
|||
|
|
@ -0,0 +1,24 @@
|
|||
/*
|
||||
* Copyright (c) 2020, ARM Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*
|
||||
* The Arm Ltd. FPGA images start execution at address 0x0, which is
|
||||
* mapped at an (emulated) ROM image. The payload uploader can write to
|
||||
* this memory, but write access by the CPU cores is prohibited.
|
||||
*
|
||||
* Provide a simple trampoline to start BL31 execution at the actual
|
||||
* load address. We put the DTB address in x0, so any code in DRAM could
|
||||
* make use of that information (not yet used in BL31 right now).
|
||||
*/
|
||||
|
||||
#include <asm_macros.S>
|
||||
#include <common/bl_common.ld.h>
|
||||
|
||||
.text
|
||||
.global _start
|
||||
|
||||
_start:
|
||||
mov_imm x1, BL31_BASE /* beginning of DRAM */
|
||||
mov_imm x0, FPGA_PRELOADED_DTB_BASE
|
||||
br x1
|
||||
Loading…
Reference in New Issue