From 632ab3eb26fcef5561cc3d0314886fd9b2793c1f Mon Sep 17 00:00:00 2001 From: Louis Mayencourt Date: Thu, 18 Apr 2019 14:34:11 +0100 Subject: [PATCH] Neoverse N1: Forces cacheable atomic to near This patch forces all cacheable atomic instructions to be near, which improves performance in highly contended parallelized use-cases. Change-Id: I93fac62847f4af8d5eaaf3b52318c30893e947d3 Signed-off-by: Louis Mayencourt --- include/lib/cpus/aarch64/neoverse_n1.h | 15 +++++++++++++-- lib/cpus/aarch64/neoverse_n1.S | 6 ++++++ 2 files changed, 19 insertions(+), 2 deletions(-) diff --git a/include/lib/cpus/aarch64/neoverse_n1.h b/include/lib/cpus/aarch64/neoverse_n1.h index 908993e45..ed5f136dd 100644 --- a/include/lib/cpus/aarch64/neoverse_n1.h +++ b/include/lib/cpus/aarch64/neoverse_n1.h @@ -13,10 +13,9 @@ #define NEOVERSE_N1_MIDR U(0x410fd0c0) /******************************************************************************* - * CPU Extended Control register specific definitions. + * CPU Power Control register specific definitions. ******************************************************************************/ #define NEOVERSE_N1_CPUPWRCTLR_EL1 S3_0_C15_C2_7 -#define NEOVERSE_N1_CPUECTLR_EL1 S3_0_C15_C1_4 /* Definitions of register field mask in NEOVERSE_N1_CPUPWRCTLR_EL1 */ #define NEOVERSE_N1_CORE_PWRDN_EN_MASK U(0x1) @@ -26,6 +25,18 @@ #define NEOVERSE_N1_AMU_NR_COUNTERS U(5) #define NEOVERSE_N1_AMU_GROUP0_MASK U(0x1f) +/******************************************************************************* + * CPU Extended Control register specific definitions. + ******************************************************************************/ +#define NEOVERSE_N1_CPUECTLR_EL1 S3_0_C15_C1_4 + +/******************************************************************************* + * CPU Auxiliary Control register specific definitions. + ******************************************************************************/ +#define NEOVERSE_N1_CPUACTLR2_EL1 S3_0_C15_C1_1 + +#define NEOVERSE_N1_CPUACTLR2_EL1_BIT_2 (ULL(1) << 2) + /* Instruction patching registers */ #define CPUPSELR_EL3 S3_6_C15_C8_0 #define CPUPCR_EL3 S3_6_C15_C8_1 diff --git a/lib/cpus/aarch64/neoverse_n1.S b/lib/cpus/aarch64/neoverse_n1.S index 060c625d4..ce63899a7 100644 --- a/lib/cpus/aarch64/neoverse_n1.S +++ b/lib/cpus/aarch64/neoverse_n1.S @@ -50,6 +50,12 @@ func neoverse_n1_reset_func /* Disables speculative loads */ msr SSBS, xzr + /* Forces all cacheable atomic instructions to be near */ + mrs x0, NEOVERSE_N1_CPUACTLR2_EL1 + orr x0, x0, #NEOVERSE_N1_CPUACTLR2_EL1_BIT_2 + msr NEOVERSE_N1_CPUACTLR2_EL1, x0 + isb + bl cpu_get_rev_var mov x18, x0