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intel: Modify non secure access function 

Combine both peripheral and bridge non-secure access code
into a single callable function

Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: I38d335ed8d1e9f55d337b63cca121a473897ef70
This commit is contained in:
Hadi Asyrafi 2019-10-21 16:27:29 +08:00 committed by Abdul Halim, Muhammad Hadi Asyrafi
parent 5d3ee0764b
commit 222519a0ea
5 changed files with 31 additions and 2 deletions
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1
plat/intel/soc/agilex/bl2_plat_setup.c
View File

@ -74,7 +74,6 @@ void bl2_el3_early_platform_setup(u_register_t x0, u_register_t x1,
socfpga_delay_timer_init();
init_ncore_ccu();
init_hard_memory_controller();
enable_ns_bridge_access();
}

3
plat/intel/soc/agilex/include/agilex_system_manager.h
View File

@ -66,6 +66,7 @@
#define AGX_CCU_NOC_IOM_RAMSPACE0_0 0xf7018628
#define AGX_SYSMGR_CORE(x) (0xffd12000 + (x))
#define SYSMGR_BOOT_SCRATCH_COLD_0 0x200
#define SYSMGR_BOOT_SCRATCH_COLD_1 0x204
#define SYSMGR_BOOT_SCRATCH_COLD_2 0x208
@ -73,6 +74,8 @@
#define DISABLE_BRIDGE_FIREWALL 0x0ffe0101
#define DISABLE_L4_FIREWALL (BIT(0) | BIT(16) | BIT(24))
void enable_nonsecure_access(void);
void enable_ns_peripheral_access(void);
void enable_ns_bridge_access(void);
#endif

6
plat/intel/soc/agilex/soc/agilex_system_manager.c
View File

@ -10,6 +10,12 @@
#include "agilex_system_manager.h"
void enable_nonsecure_access(void)
{
enable_ns_peripheral_access();
enable_ns_bridge_access();
}
void enable_ns_peripheral_access(void)
{
mmio_write_32(AGX_NOC_FW_L4_PER_SCR_NAND_REGISTER, DISABLE_L4_FIREWALL);
mmio_write_32(AGX_NOC_FW_L4_PER_SCR_NAND_DATA, DISABLE_L4_FIREWALL);

12
plat/intel/soc/stratix10/include/s10_system_manager.h
View File

@ -4,6 +4,10 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
#define S10_FIREWALL_SOC2FPGA 0xffd21200
#define S10_FIREWALL_LWSOC2FPGA 0xffd21300
/* L3 Interconnect Register Map */
#define S10_NOC_FW_L4_PER_SCR_NAND_REGISTER 0xffd21000
#define S10_NOC_FW_L4_PER_SCR_NAND_DATA 0xffd21004
#define S10_NOC_FW_L4_PER_SCR_USB0_REGISTER 0xffd2100c
@ -59,13 +63,19 @@
#define S10_CCU_NOC_CPU0_RAMSPACE0_0 0xf7004688
#define S10_CCU_NOC_IOM_RAMSPACE0_0 0xf7018628
/* System Manager Register Map */
#define S10_SYSMGR_CORE(x) (0xffd12000 + (x))
#define SYSMGR_MMC 0x28
#define SYSMGR_MMC_DRVSEL(x) (((x) & 0x7) << 0)
#define SYSMGR_BOOT_SCRATCH_COLD_0 0x200
#define SYSMGR_BOOT_SCRATCH_COLD_1 0x204
#define SYSMGR_BOOT_SCRATCH_COLD_2 0x208
#define DISABLE_BRIDGE_FIREWALL 0x0ffe0101
#define DISABLE_L4_FIREWALL (BIT(0) | BIT(16) | BIT(24))
void enable_nonsecure_access(void);
void enable_ns_peripheral_access(void);
void enable_ns_bridge_access(void);

11
plat/intel/soc/stratix10/soc/s10_system_manager.c
View File

@ -9,6 +9,12 @@
#include "s10_system_manager.h"
void enable_nonsecure_access(void)
{
enable_ns_peripheral_access();
enable_ns_bridge_access();
}
void enable_ns_peripheral_access(void)
{
mmio_write_32(S10_NOC_FW_L4_PER_SCR_NAND_REGISTER, DISABLE_L4_FIREWALL);
mmio_write_32(S10_NOC_FW_L4_PER_SCR_NAND_DATA, DISABLE_L4_FIREWALL);
@ -91,3 +97,8 @@ void enable_nonsecure_access(void)
}
void enable_ns_bridge_access(void)
{
mmio_write_32(S10_FIREWALL_SOC2FPGA, DISABLE_BRIDGE_FIREWALL);
mmio_write_32(S10_FIREWALL_LWSOC2FPGA, DISABLE_BRIDGE_FIREWALL);
}